Author: rminnich Date: 2008-08-13 04:49:03 +0200 (Wed, 13 Aug 2008) New Revision: 754
Modified: coreboot-v3/mainboard/gigabyte/Kconfig coreboot-v3/mainboard/gigabyte/m57sli/Makefile coreboot-v3/mainboard/gigabyte/m57sli/dts coreboot-v3/mainboard/gigabyte/m57sli/initram.c coreboot-v3/mainboard/gigabyte/m57sli/stage1.c Log: yea, it's ugly, but I want to get it in. It's a work in progress. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com Acked-by: Marc Jones marc.jones@amd.com
Modified: coreboot-v3/mainboard/gigabyte/Kconfig =================================================================== --- coreboot-v3/mainboard/gigabyte/Kconfig 2008-08-13 02:44:46 UTC (rev 753) +++ coreboot-v3/mainboard/gigabyte/Kconfig 2008-08-13 02:49:03 UTC (rev 754) @@ -31,6 +31,7 @@ select NORTHBRIDGE_AMD_K8 select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_ITE_IT8716F + select IOAPIC help Gigabyte M57SLI
Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-13 02:44:46 UTC (rev 753) +++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-13 02:49:03 UTC (rev 754) @@ -20,17 +20,19 @@ ##
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \ - $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c \ + $(obj)/mainboard/$(MAINBOARDDIR)/option_table.o \ $(obj)/southbridge/nvidia/mcp55/stage1_smbus.o \ - $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ - $(obj)/northbridge/amd/k8/raminit.o \ $(obj)/northbridge/amd/k8/coherent_ht.o \ - $(obj)/northbridge/amd/k8/incoherent_ht.o + $(obj)/northbridge/amd/k8/incoherent_ht.o \ + $(obj)/lib/clog2.o
-# I can't get this to work -- if you can fix it do so. The file above -# from "initram" on should be here. -INITRAM_SRC= +INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/k8/raminit.c \ + $(src)/arch/x86/pci_ops_conf1.c \ + $(src)/southbridge/nvidia/mcp55/stage1_smbus.c \ + $(src)/lib/clog2.c
+ STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
Modified: coreboot-v3/mainboard/gigabyte/m57sli/dts =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/dts 2008-08-13 02:44:46 UTC (rev 753) +++ coreboot-v3/mainboard/gigabyte/m57sli/dts 2008-08-13 02:49:03 UTC (rev 754) @@ -17,6 +17,25 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/*00:00.0 RAM memory: nVidia Corporation MCP55 Memory Controller (rev a1) +00:01.0 ISA bridge: nVidia Corporation MCP55 LPC Bridge (rev a2) +00:01.1 SMBus: nVidia Corporation MCP55 SMBus (rev a2) +00:02.0 USB Controller: nVidia Corporation MCP55 USB Controller (rev a1) +00:02.1 USB Controller: nVidia Corporation MCP55 USB Controller (rev a2) +00:04.0 IDE interface: nVidia Corporation MCP55 IDE (rev a1) +00:05.0 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) +00:05.1 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) +00:06.0 PCI bridge: nVidia Corporation MCP55 PCI bridge (rev a2) +00:06.1 Audio device: nVidia Corporation MCP55 High Definition Audio (rev a2) +00:08.0 Bridge: nVidia Corporation MCP55 Ethernet (rev a2) +00:0f.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) +00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map +00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller +00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control +01:0a.0 FireWire (IEEE 1394): Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) +02:00.0 VGA compatible controller: nVidia Corporation G72 [GeForce 7300 LE] (rev a1) +*/
/{ mainboard_vendor = "Gigabyte"; @@ -25,8 +44,16 @@ apic@0 { }; domain@0 { + pci@1,0{ + }; pci@18,0 { /config/("northbridge/amd/k8/pci"); + pci@0,0 { + /config/("southbridge/nvidia/mcp55/ide.dts"); + }; + pci@0,1 { + /config/("southbridge/nvidia/mcp55/sata.dts"); + }; }; }; };
Modified: coreboot-v3/mainboard/gigabyte/m57sli/initram.c =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-08-13 02:44:46 UTC (rev 753) +++ coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-08-13 02:49:03 UTC (rev 754) @@ -31,8 +31,28 @@ #include <io.h> #include <cpu.h> #include <amd/k8/k8.h> +#include <southbridge/nvidia/mcp55/mcp55_smbus.h> +#include <mc146818rtc.h> #include <spd.h>
+# warning fix hard_reset +void hard_reset(void) +{ +} +void memreset_setup(void) +{ +} + +void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} + + /** * main for initram for the Gigabyte m57sli. */
Modified: coreboot-v3/mainboard/gigabyte/m57sli/stage1.c =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-08-13 02:44:46 UTC (rev 753) +++ coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-08-13 02:49:03 UTC (rev 754) @@ -32,20 +32,7 @@ #include <io.h> #include <arch/x86/msr.h>
-void memreset_setup(void) -{ -}
-void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - - void hardware_stage1(void) { post_code(POST_START_OF_MAIN);