2007/5/31, Juergen Beisert juergen127@kreuzholzen.de:
Maybe a silly question: Isn't it that PCI needs initialization before we could access it? How could we get there when the processor is fetching the 1st instruction?
In this case the ROM device is connected to the PCI bus, but not connected _as_ a PCI device!. It shares the PCI bus address/data lines only to save an additional bus. If you reuse (or misuse?) the AD[31...0] lines you can connect up to a 16MiB ROM device with 8 bit data width (AD[31...8] as addressbus, AD[7..0] as data bus). Add also three separate additional lines (read, write, chip select) and you are done. Whenever the chipset generates a ROM device access cycle, it does not generate a valid PCI cycle as it only uses the AD[31...0] lines! So this does not hurt any other *real* PCI device on the same bus. But this may work only at system start. Later on some PCI master devices could inhibit this mode. But it doesn't matter: At this point of time the ROM content runs from system RAM, so there is no more need to access the real ROM device (maybe only to reprogramm it).
Hope it helps.
Juergen
Please check whether I have understood correctly.
The processor lauches a cycle with address = 0xFFFF_FFF0. The north bridge chipset explains this address. In this case, it signals the read line and chip select line which connect the ROM device, and select an address of the ROM device through PCI bus AD[31..8]. To the north bridge, the ROM device is like a common BIOS ROM except that it uses PCI bus to exchange information. Then the ROM device uses AD[7..0] to send 1 byte of data back to the north bridge. That 1 byte of data is a portion of the 1st instruction.
Thanks.
Yu-ning