[coreboot] Re: Problems with CAR setup on Tiger Lake

[Michał Żygowski]

On 1/19/21 5:10 PM, Tim Wawrzynczak via coreboot wrote:
> Dear Michał,
>
> Do you have a config for us to look at for your board? Are you
> using INTEL_CAR_NEM_ENHANCED ?

Hi Tim,

Sure, see attached, yes INTEL_CAR_NEM_ENHANCED is selected.
> Based on the post code you observed last, I might guess that you
> overfilled the cache when doing the cache fill
> operation, e.g. the next few lines in cache_as_ram.S after post-code
> 0x26; doing so will cause a MCE.
> Do you know how much data you're trying to place in the cache
> (CONFIG_DCACHE_RAM_SIZE) and also how much LLC your SKU has?

Not sure about LLC size, but yeah, caching whole SPI (32MB) may be too
big. Maybe this is the problem. This is a Super SKU.
CONFIG_DCACHE_RAM_SIZE=0x80000
> FYI, Tiger Lake has some new requirements for CAR setup when using
> eNEM mode, which
> should be taken care of by the default soc/intel/tigerlake/Kconfig
> file. Do you have local changes to that?

No changes except the FMD layout to give more space for
COREBOOT/FW_MAIN_A/FW_MAIN_B by sacrificing RW_LEGACY.
> You can also see mb/google/volteer for an example of a functional TGL
> coreboot board, feel free to ask me
> any other questions you have.

Will visit it and check it.
> Cheers,
>  - Tim

Regards,