On 10/31/2019 3:08 AM, Michal Zygowski wrote:
I'm not blaming Intel. As you said Nate, there is nothing you can do. Just pointing out that "vendors are creating tons of forks" where by vendor I had IBVs in mind (in some particular cases Intel may be an IBV, but this time I implicitly excluded Intel as IBV, sorry I didn't clarify).
Regards, Michał
We are very aware of this issue, and we are trying very hard to reduce fragmentation in the firmware ecosystem for products based on Intel platforms.
Just to give a little more context on this, none of the IBVs actually implement the memory code from scratch anymore. Starting roughly in the Westmere/Sandy Bridge time-frame, everyone took Intel's memory code as a baseline and then started modifying on top of that. Starting with Haswell, that expanded from just memory code to all of the SOC initialization code. Also starting with Haswell, we changed our message that modification of the SOC initialization code was actively discouraged. Conversely, we actively encouraged upsteaming of changes in the SOC initialization code back to Intel. This shift created the preconditions necessary for the FSP to be created. The next big change came with Sky Lake, where we made a requirement that all the BIOS vendors moved from their custom implementation of EDK1 to the single open source EDK2 implementation developed by the TianoCore project.
For the newer Intel SOCs, there should be very little difference between the memory code provided by Intel and the memory code provided by other BIOS vendors. That said, we have noticed that some of the BIOS vendors hoard bugs.
Fast forward to today, we are encouraging all BIOS vendors to not only use FSP, but to use FSP binaries published by Intel directly. If and when we reach that goal, then the issues you mention about some BIOS vendors having a different fork of the memory code than what FSP has should go away.
In parallel, one of the primary criticisms of the TianoCore project is that nobody contributes a complete firmware implementation, just bits and pieces. We are working hard to change that. We have a new sub-project in TianoCore called "Minimum Platform" which aims to provide a complete, open source, lightweight, and modular UEFI firmware implementation purely based on EDK2 and FSP. Unlike past efforts, we are focused on hardware that you can actually buy, not just Intel reference boards or difficult to acquire small board computers. We are trying to build something that is actually useful for the community. Its still alpha stage at the moment; and we only have 6 motherboards and 3 chipsets supported thus far but we are trying to grow that list. If you are interested, here is the overview: https://osfc.io/talks/minimum-platform-open-source-uefi-firmware-for-intel-b... and the code: https://github.com/tianocore/edk2-platforms/tree/master/Platform/Intel . In time, our hope is that Minimum Platform provides a viable alternative for the industry.
With Best Regards,
Nate
Applying the same changed SPD parameters may give different results of memory training with FSP and vendor BIOS. The best way to go is to get the hands on the papers David pointed to (if possible) and do trial-by-error. It may take time but there is a chance to succeed. Good thing is you have debug output from FSP so at least you know what is wrong.
Regards, Michał
I found that the flag called FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT is there which I can make use of, to pass an SPD bin. I am not sure how to prepare that binary but I am assuming we can put all the 512 hex bytes of SPD as per DDR4 SPD spec into a text file and name it as spd.bin and pass along. (example : https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/cannonl...) Coreboot build system will automatically pack it. Compilation passed for me and will test it now, if the SPD data is read properly. https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex
coreboot/coreboot https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex github mirror of coreboot.org's master repository. Contribute to coreboot/coreboot development by creating an account on GitHub. github.com
In case this is not the correct way, the alternative way could be to create a UINT8 buff [512] and typecast to UpdData->MemDownCh0Dimm0SpdPtr = (UINT32) buff; directly.
While I am testing all this, anyone please correct me on the .bin part, so that it helps future contributors as well, as its not documented anywhere in coreboot.
Regards, Naveen
*From:* David Hendricks david.hendricks@gmail.com *Sent:* Wednesday, 30 October, 2019, 12:44 PM *To:* Naveen Chaudhary *Cc:* Wim Vervoorn; Nico Huber; coreboot@coreboot.org *Subject:* Re: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration not in POR table"
Hi Naveen, Yes, the first sentence. The DIMMs you are using appear to have geometry or timings incompatible with Broadwell-DE, based on the SPD values that the vendor programmed. Chapter 6 of the PDG (docid 543448) should help clarify what kinds of DIMMs are supported and how they should be populated.
On Tue, Oct 29, 2019 at 5:07 AM Naveen Chaudhary <naveenchaudhary2010@hotmail.com mailto:naveenchaudhary2010@hotmail.com> wrote:
Sorry I didn't get the point completely. Do you mean the settings are not compatible with FSP code? Or do you mean the settings might be conflicting themselves. Since the above settings were read from SPD and the chip vendor must have definitely set them correctly, I assume you meant first sentence. Please correct me. Regards, Naveen Get Outlook for Android <https://aka.ms/ghei36> ------------------------------------------------------------------------ *From:* Wim Vervoorn <wvervoorn@eltan.com <mailto:wvervoorn@eltan.com>> *Sent:* Tuesday, October 29, 2019 3:47:34 PM *To:* Naveen Chaudhary <naveenchaudhary2010@hotmail.com <mailto:naveenchaudhary2010@hotmail.com>>; Nico Huber <nico.h@gmx.de <mailto:nico.h@gmx.de>>; David Hendricks <david.hendricks@gmail.com <mailto:david.hendricks@gmail.com>> *Cc:* coreboot@coreboot.org <mailto:coreboot@coreboot.org> <coreboot@coreboot.org <mailto:coreboot@coreboot.org>> *Subject:* RE: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration not in POR table" Hello Naveen, This is the important part. This indicates the what you selected is not supported. Please review your settings carefully. This isn't a single check. The code validates the SPD settings against the other settings you made. So please make sure you are passing in a DDR4 SPD when you select DDR4 mode. Also please make sure the SPD settings are in The list of supported configuration for the chip. Check POR Compatibility -- Started primaryWidthDDR4: 1, rowBitsDDR4: 16, columnBitsDDR4: 10, bankGroupsDDR4: 4 primaryWidthDDR4: 1, rowBitsDDR4: 16, columnBitsDDR4: 10, bankGroupsDDR4: 4 Unknown DIMM population ***** Check POR Compatibility - 17ms Initialize DDR Clocks -- Started Checkpoint Code: Socket 0, 0xB1, 0x00, 0x0000 Configuration not in POR table! *** (This basically indicates you are trying to do something that is not supported by the chipset). Best regards, Wim *From:*Naveen Chaudhary [mailto:naveenchaudhary2010@hotmail.com <mailto:naveenchaudhary2010@hotmail.com>] *Sent:* Tuesday, October 29, 2019 10:44 AM *To:* Wim Vervoorn <wvervoorn@eltan.com <mailto:wvervoorn@eltan.com>>; Nico Huber <nico.h@gmx.de <mailto:nico.h@gmx.de>>; David Hendricks <david.hendricks@gmail.com <mailto:david.hendricks@gmail.com>> *Cc:* coreboot@coreboot.org <mailto:coreboot@coreboot.org> *Subject:* Re: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration not in POR table" Thanks Wim. I will give a try and pass a 512 byte hex block corresponding to the SPD data and if it works, I can play with the hex values to find out the right configuration. BTW, any idea which field can impact the ddrfreq which was reported as error in the initial logs? Regards, Naveen Get Outlook for Android <https://aka.ms/ghei36> ------------------------------------------------------------------------ *From:*Wim Vervoorn <wvervoorn@eltan.com <mailto:wvervoorn@eltan.com>> *Sent:* Tuesday, October 29, 2019 3:07:44 PM *To:* Nico Huber <nico.h@gmx.de <mailto:nico.h@gmx.de>>; Naveen Chaudhary <naveenchaudhary2010@hotmail.com <mailto:naveenchaudhary2010@hotmail.com>>; David Hendricks <david.hendricks@gmail.com <mailto:david.hendricks@gmail.com>> *Cc:* coreboot@coreboot.org <mailto:coreboot@coreboot.org> <coreboot@coreboot.org <mailto:coreboot@coreboot.org>> *Subject:* RE: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration not in POR table" Hello Naveen, You should use the "MemDownCh0Dimm0SpdPtr" to point to a buffer containing the SPD data and set MemDownEnable" to 1. Best Regards, Wim Vervoorn -----Original Message----- From: Nico Huber [mailto:nico.h@gmx.de] Sent: Sunday, October 27, 2019 11:33 AM To: Naveen Chaudhary <naveenchaudhary2010@hotmail.com <mailto:naveenchaudhary2010@hotmail.com>>; David Hendricks <david.hendricks@gmail.com <mailto:david.hendricks@gmail.com>> Cc: coreboot@coreboot.org <mailto:coreboot@coreboot.org> Subject: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration not in POR table" Hello Naveen, On 27.10.19 05:02, Naveen Chaudhary wrote: > Does this mean that there is a way in FSP to define custom settings(configs) for DIMMs? In the FSP integration guide for BroadwellDE (https://github.com/IntelFsp/FSP/tree/master/BroadwellDEFspBinPkg/Docs) I don't see any relevant data member where we could define pointer to custom SPD settings or pass individual DIMMs configurations. there is the memory-down option. It seems undocumented if that does more than switching from on-DIMM SPDs to SPD files. Maybe it's worth a try. If that doesn't work out, you can always overwrite the SPDs on your DIMM's EEPROMs. Always keep a backup, though. Hope that helps, Nico _______________________________________________ coreboot mailing list -- coreboot@coreboot.org <mailto:coreboot@coreboot.org> To unsubscribe send an email to coreboot-leave@coreboot.org <mailto:coreboot-leave@coreboot.org>
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