Author: stepan Date: Sun May 30 14:33:12 2010 New Revision: 5597 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5597
Log: Added support to ICH9 chipset family Signed-off-by: Anton Kochkov anton.kochkov@gmail.com Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: trunk/util/inteltool/gpio.c trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h trunk/util/inteltool/memory.c trunk/util/inteltool/pcie.c trunk/util/inteltool/powermgt.c trunk/util/inteltool/rootcmplx.c
Modified: trunk/util/inteltool/gpio.c ============================================================================== --- trunk/util/inteltool/gpio.c Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/gpio.c Sun May 30 14:33:12 2010 (r5597) @@ -114,6 +114,24 @@ { 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" } };
+static const io_register_t ich9_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "RESERVED" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "GP_SER_BLINK" }, + { 0x20, 4, "GP_SB_CMDSTS" }, + { 0x24, 4, "GP_SB_DATA" }, + { 0x28, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, + { 0x3C, 4, "RESERVED" } +};
int print_gpios(struct pci_dev *sb) { @@ -124,6 +142,16 @@ printf("\n============= GPIOS =============\n\n");
switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH9DH: + case PCI_DEVICE_ID_INTEL_ICH9DO: + case PCI_DEVICE_ID_INTEL_ICH9R: + case PCI_DEVICE_ID_INTEL_ICH9: + case PCI_DEVICE_ID_INTEL_ICH9M: + case PCI_DEVICE_ID_INTEL_ICH9ME: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = ich9_gpio_registers; + size = ARRAY_SIZE(ich9_gpio_registers); + break; case PCI_DEVICE_ID_INTEL_ICH8M: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich8_gpio_registers;
Modified: trunk/util/inteltool/inteltool.c ============================================================================== --- trunk/util/inteltool/inteltool.c Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/inteltool.c Sun May 30 14:33:12 2010 (r5597) @@ -45,7 +45,14 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME-GMCH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
Modified: trunk/util/inteltool/inteltool.h ============================================================================== --- trunk/util/inteltool/inteltool.h Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/inteltool.h Sun May 30 14:33:12 2010 (r5597) @@ -44,6 +44,12 @@ #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 +#define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912 +#define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914 +#define PCI_DEVICE_ID_INTEL_ICH9R 0x2916 +#define PCI_DEVICE_ID_INTEL_ICH9 0x2918 +#define PCI_DEVICE_ID_INTEL_ICH9M 0x2919 +#define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
#define PCI_DEVICE_ID_INTEL_82810 0x7120 @@ -58,10 +64,10 @@ #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0 #define PCI_DEVICE_ID_INTEL_82G33 0x29c0 #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 +#define PCI_DEVICE_ID_INTEL_GS45 0x2a40 #define PCI_DEVICE_ID_INTEL_X58 0x3405
#define PCI_DEVICE_ID_INTEL_82443LX 0x7180 - /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ #define PCI_DEVICE_ID_INTEL_82443BX 0x7190 #define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192
Modified: trunk/util/inteltool/memory.c ============================================================================== --- trunk/util/inteltool/memory.c Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/memory.c Sun May 30 14:33:12 2010 (r5597) @@ -54,6 +54,10 @@ case PCI_DEVICE_ID_INTEL_82830M: printf("This northbrigde does not have MCHBAR.\n"); return 1; + case PCI_DEVICE_ID_INTEL_GS45: + mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; default: printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); return 1;
Modified: trunk/util/inteltool/pcie.c ============================================================================== --- trunk/util/inteltool/pcie.c Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/pcie.c Sun May 30 14:33:12 2010 (r5597) @@ -43,6 +43,7 @@ case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_GS45: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -95,12 +96,12 @@ case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_GS45: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; break; case PCI_DEVICE_ID_INTEL_82810: case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82830M: printf("This northbrigde does not have DMIBAR.\n"); return 1; default: @@ -149,6 +150,7 @@ case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_GS45: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break;
Modified: trunk/util/inteltool/powermgt.c ============================================================================== --- trunk/util/inteltool/powermgt.c Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/powermgt.c Sun May 30 14:33:12 2010 (r5597) @@ -21,47 +21,47 @@ #include <stdio.h> #include "inteltool.h"
-static const io_register_t ich7_pm_registers[] = { - { 0x00, 2, "PM1_STS" }, - { 0x02, 2, "PM1_EN" }, - { 0x04, 4, "PM1_CNT" }, - { 0x08, 4, "PM1_TMR" }, +static const io_register_t ich9_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK + { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2 + { 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK + { 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK { 0x0c, 4, "RESERVED" }, - { 0x10, 4, "PROC_CNT" }, + { 0x10, 4, "PROC_CNT" }, // Processor Control; ACPI pointer: P_BLK #if DANGEROUS_REGISTERS /* These registers return 0 on read, but reading them may cause - * the system to enter C2/C3/C4 state, which might hang the system. + * the system to enter Cx states, which might hang the system. */ - { 0x14, 1, "LV2 (Mobile/Ultra Mobile)" }, - { 0x15, 1, "LV3 (Mobile/Ultra Mobile)" }, - { 0x16, 1, "LV4 (Mobile/Ultra Mobile)" }, + { 0x14, 1, "LV2 (Mobile)" }, + { 0x15, 1, "LV3 (Mobile)" }, + { 0x16, 1, "LV4 (Mobile)" }, + { 0x17, 1, "LV5 (Mobile)" }, + { 0x18, 1, "LV6 (Mobile)" }, #endif - { 0x17, 1, "RESERVED" }, - { 0x18, 4, "RESERVED" }, + { 0x19, 1, "RESERVED" }, + { 0x1a, 2, "RESERVED" }, { 0x1c, 4, "RESERVED" }, - { 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" }, - { 0x21, 1, "RESERVED" }, - { 0x22, 2, "RESERVED" }, - { 0x24, 4, "RESERVED" }, - { 0x28, 4, "GPE0_STS" }, - { 0x2C, 4, "GPE0_EN" }, + { 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK + { 0x2C, 4, "GPE0_EN" }, // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8 { 0x30, 4, "SMI_EN" }, { 0x34, 4, "SMI_STS" }, { 0x38, 2, "ALT_GP_SMI_EN" }, { 0x3a, 2, "ALT_GP_SMI_STS" }, - { 0x3c, 4, "RESERVED" }, + { 0x3c, 1, "UPRWC" }, // USB Per-Port registers write control; + { 0x3d, 2, "RESERVED" }, + { 0x3f, 1, "RESERVED" }, { 0x40, 2, "RESERVED" }, { 0x42, 1, "GPE_CNTL" }, { 0x43, 1, "RESERVED" }, - { 0x44, 2, "DEVACT_STS" }, + { 0x44, 2, "DEVACT_STS" }, // Device Activity Status { 0x46, 2, "RESERVED" }, { 0x48, 4, "RESERVED" }, { 0x4c, 4, "RESERVED" }, - { 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" }, + { 0x50, 1, "PM2_CNT (Mobile)" }, // PM2 Control (Mobile only); ACPI pointer: PM2a_CNT_BLK { 0x51, 1, "RESERVED" }, { 0x52, 2, "RESERVED" }, - { 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" }, - { 0x58, 4, "RESERVED" }, + { 0x54, 4, "C3_RES (Mobile)" }, + { 0x58, 4, "C5_RES (Mobile)" }, { 0x5c, 4, "RESERVED" }, /* Here start the TCO registers */ { 0x60, 2, "TCO_RLD" }, @@ -145,6 +145,67 @@ { 0x7c, 4, "RESERVED" }, };
+static const io_register_t ich7_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, + { 0x02, 2, "PM1_EN" }, + { 0x04, 4, "PM1_CNT" }, + { 0x08, 4, "PM1_TMR" }, + { 0x0c, 4, "RESERVED" }, + { 0x10, 4, "PROC_CNT" }, +#if DANGEROUS_REGISTERS + /* These registers return 0 on read, but reading them may cause + * the system to enter C2/C3/C4 state, which might hang the system. + */ + { 0x14, 1, "LV2 (Mobile/Ultra Mobile)" }, + { 0x15, 1, "LV3 (Mobile/Ultra Mobile)" }, + { 0x16, 1, "LV4 (Mobile/Ultra Mobile)" }, +#endif + { 0x17, 1, "RESERVED" }, + { 0x18, 4, "RESERVED" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" }, + { 0x21, 1, "RESERVED" }, + { 0x22, 2, "RESERVED" }, + { 0x24, 4, "RESERVED" }, + { 0x28, 4, "GPE0_STS" }, + { 0x2C, 4, "GPE0_EN" }, + { 0x30, 4, "SMI_EN" }, + { 0x34, 4, "SMI_STS" }, + { 0x38, 2, "ALT_GP_SMI_EN" }, + { 0x3a, 2, "ALT_GP_SMI_STS" }, + { 0x3c, 4, "RESERVED" }, + { 0x40, 2, "RESERVED" }, + { 0x42, 1, "GPE_CNTL" }, + { 0x43, 1, "RESERVED" }, + { 0x44, 2, "DEVACT_STS" }, + { 0x46, 2, "RESERVED" }, + { 0x48, 4, "RESERVED" }, + { 0x4c, 4, "RESERVED" }, + { 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" }, + { 0x51, 1, "RESERVED" }, + { 0x52, 2, "RESERVED" }, + { 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" }, + { 0x58, 4, "RESERVED" }, + { 0x5c, 4, "RESERVED" }, + /* Here start the TCO registers */ + { 0x60, 2, "TCO_RLD" }, + { 0x62, 1, "TCO_DAT_IN" }, + { 0x63, 1, "TCO_DAT_OUT" }, + { 0x64, 2, "TCO1_STS" }, + { 0x66, 2, "TCO2_STS" }, + { 0x68, 2, "TCO1_CNT" }, + { 0x6a, 2, "TCO2_CNT" }, + { 0x6c, 2, "TCO_MESSAGE" }, + { 0x6e, 1, "TCO_WDCNT" }, + { 0x6f, 1, "RESERVED" }, + { 0x70, 1, "SW_IRQ_GEN" }, + { 0x71, 1, "RESERVED" }, + { 0x72, 2, "TCO_TMR" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, +}; + /* * INTEL I/O Controller Hub 6 Family * http://www.intel.com/assets/pdf/datasheet/301473.pdf @@ -357,6 +418,16 @@ pm_registers = ich7_pm_registers; size = ARRAY_SIZE(ich7_pm_registers); break; + case PCI_DEVICE_ID_INTEL_ICH9DH: + case PCI_DEVICE_ID_INTEL_ICH9DO: + case PCI_DEVICE_ID_INTEL_ICH9R: + case PCI_DEVICE_ID_INTEL_ICH9: + case PCI_DEVICE_ID_INTEL_ICH9M: + case PCI_DEVICE_ID_INTEL_ICH9ME: + pmbase = pci_read_word(sb, 0x40) & 0xfffc; + pm_registers = ich9_pm_registers; + size = ARRAY_SIZE(ich9_pm_registers); + break; case PCI_DEVICE_ID_INTEL_ICH8M: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich8_pm_registers;
Modified: trunk/util/inteltool/rootcmplx.c ============================================================================== --- trunk/util/inteltool/rootcmplx.c Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/rootcmplx.c Sun May 30 14:33:12 2010 (r5597) @@ -36,6 +36,12 @@ case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_ICH9DH: + case PCI_DEVICE_ID_INTEL_ICH9DO: + case PCI_DEVICE_ID_INTEL_ICH9R: + case PCI_DEVICE_ID_INTEL_ICH9: + case PCI_DEVICE_ID_INTEL_ICH9M: + case PCI_DEVICE_ID_INTEL_ICH9ME: case PCI_DEVICE_ID_INTEL_ICH8M: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break;