Thanks Matt
Using your instructions I was able to get these files:
cpu_microcode_blob.bin flashdescriptor.bin fspm.bin fsps.bin hashes.txt me.bin vbt.bin
I wasn't sure the difference between fspm and fsps, but running strings on fspm.bin I see "Jasper Lake processor and Jasper Lake PCH".
The only other error is "coreboot has been built without an Intel Firmware Descriptor."
So far as I can tell, as long as I run ./ifdtool -f layout <original BIOS file> and use the BIOS section there, I'm ok?
I get a warning doing that "Warning: No platform specified. Output may be incomplete", but I do at least get the BIOS offsets.
Thanks again for your help.
Marcos
On Thu, 25 May 2023, at 04:38, Matt DeVillier wrote:
Since there are no official FSP binaries for JasperLake available, the best you can do is use the Google ones extracted from a ChromeOS device firmware image.
Luckily, there are scripts in the coreboot repo to do just that:
cd util/chromeos bash crosfirmware.sh sasuke #name of a JSL ChromeOS board I know will work bash extract_blobs.sh <filename produced by command above> # will be named coreboot-Google_[board name].[version string].bin
As this is downloading and extracting a ChromeOS recovery image, you'll need about 10GB free space to do this (though the script cleans up after itself).
On Wed, May 24, 2023 at 4:20 PM Marcos Scriven marcos@scriven.org wrote:
Hello all
I'd like to get Coreboot working on a new target device, so I'll follow the 6 steps in the https://www.coreboot.org/FAQ section entitled "Will coreboot work on my machine?" It looks like someone emailed the mailing list about this back in November '22 https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/I5HFQ..., but if I'm reading the archive correctly, didn't get any responses.
Step 1: A very brief description of your system: board vendor, board name, CPU, northbridge, southbridge, and optionally other important details.
Board Vendor: Board is branded Topton, but the board is from CWWK. CWWK mentions this board on one of their firmware update pages https://www.changwang.com/down/74.html Board Name: MW-JSL2.5G4L CPU: N5105 North Bridge Intel Jasper Lake Host Bridge rev 00 South Bridge Intel Jasper Lake PCH rev 01
• Step 2: Linux "*lspci -tvnn*" output for your system, generated by booting Linux via the original BIOS and runnning lspci.
-[0000:00]-+-00.0 Intel Corporation Device [8086:4e24] +-02.0 Intel Corporation Device [8086:4e61] +-04.0 Intel Corporation Device [8086:4e03] +-14.0 Intel Corporation Device [8086:4ded] +-14.2 Intel Corporation Device [8086:4def] +-15.0 Intel Corporation Device [8086:4de8] +-15.2 Intel Corporation Device [8086:4dea] +-16.0 Intel Corporation Device [8086:4de0] +-17.0 Intel Corporation Device [8086:4dd3] +-19.0 Intel Corporation Device [8086:4dc5] +-19.1 Intel Corporation Device [8086:4dc6] +-1c.0-[01]----00.0 Phison Electronics Corporation E12 NVMe Controller [1987:5012] +-1c.4-[02]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.5-[03]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.6-[04]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.7-[05]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1e.0 Intel Corporation Device [8086:4da8] +-1e.3 Intel Corporation Device [8086:4dab] +-1f.0 Intel Corporation Device [8086:4d87] +-1f.3 Intel Corporation Device [8086:4dc8] +-1f.4 Intel Corporation Device [8086:4da3] -1f.5 Intel Corporation Device [8086:4da4]
• Step 3: Super I/O chip on the mainboard (report the model numbers on the actual chip, for example "Winbond W83627HF" and/or run "*superiotool https://www.coreboot.org/Superiotool -dV*").
Output of superiotool -dV (minus all the probing/failed):
Found ITE IT8613E (id=0x8613, rev=0xc) at 0x2e Register dump: idx 20 21 22 23 24 2b val 86 13 0c 40 00 48 def 86 13 05 40 00 48 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 01 def 00 03 f8 04 00 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 fa fb fc val 01 0a 30 0a 20 00 80 00 00 00 20 00 f0 00 00 00 def 00 02 90 02 30 09 00 00 00 00 00 NA NA 00 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 00 00 60 00 64 01 02 48 def 01 00 60 00 64 01 02 48 LDN 0x06 (Mouse) idx 30 70 71 f0 val 00 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 2d 60 61 62 63 70 71 72 73 74 b0 b1 b2 b3 b4 b8 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc cd da db e0 e1 e2 e3 e4 ec f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb val 00 f7 80 08 d1 00 41 02 0a 10 0a 00 00 01 00 00 00 00 00 00 00 00 00 00 00 c0 03 01 06 80 48 90 00 00 00 00 00 00 b0 44 00 00 00 00 00 00 00 00 00 00 00 00 0e 00 00 00 00 00 def 00 f3 00 00 00 01 01 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA NA 00 00 0e 00 00 00 00 00 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 06
• Step 4: Type of BIOS device (see the question "How do I identify the BIOS chip on my mainboard?" below). Please send us the output of "*flashrom http://flashrom.org/ -p internal -V*"
Direct inspection shows 8-pin 16MB w25q128jv, however, flashrom doesn't seem to include that in the list of Winbond chips it probes for. dmidecode says it's an 8MB ROM, so not sure why the discrepancy
• Step 5: URL to the mainboard specifications page (optional).
Topton (branded) https://www.aliexpress.com/item/1005004374464011.html Can't find official specs, but there's a pho
• Step 6: Any other relevant information you can provide.
There's a photo of the board on the left of this BIOS update page https://www-changwang-com.translate.goog/down/74.html?_x_tr_sl=zh-CN&_x_...
I've been Googling both "Jasperlake coreboot" and "n5105 coreboot".
I see there was news of starting to support this back in January 2020 https://www.phoronix.com/news/Coreboot-JSP-TGL-Razer-ICL
Looking at some Coreboot commits, I see a "jasperlake-rvp" target was added, so I simply tried it out.
It seems to build fine, but with two warnings:
** WARNING **ADD_FSP_BINARIES isn't selected even though this SoC relies on the FSP. The resulting image won't contain the FSP binaries and will not boot unless they are added later.
** WARNING **coreboot has been built without an Intel Firmware Descriptor. Never write a complete coreboot.rom without an IFD to your board's flash chip! You can use flashrom's IFD or layout parameters to flash only to the BIOS region.
The first warning seems to suggest I can't ignore is (as it won't boot). I thus went looking for an FSP bin for this chip.
Unfortunately it doesn't seem to be in the official Intel Github repo, and there's an unanswered issue there looking for it https://github.com/intel/FSP/issues/74
I hope that provides the necessary info to make a start!
Thanks
Marcos _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org