Patch attached. I use Seamonkey and the patch applied just fine after
the roundtrip. Sorry for the inconvenience.
Thanks. The IRQ routing was copied straight from v2 so there should be
no difference in theory.
All those SMBus error messages. Need to investigate.
And the above points to memory corruption or reading uninitialized
memory. That's a bug.
Same here. And countless repetitions.
Similar bug.
Ouch. And I claim the table was a straight copy of the v2 db800 table...
Thanks a lot for testing! Could you maybe test v2 db800 as well to check
IRQ routing tables consistency there?
Fixes for some of the bugs above will come in a separate patch.
--
http://www.hailfinger.org/
--- /dev/null 2007-09-21 23:50:58.000000000 +0200
+++ LinuxBIOSv3-db800/mainboard/amd/db800/Kconfig 2008-03-04 03:07:01.000000000 +0100
@@ -0,0 +1,44 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 coresystems GmbH
+## (Written by Stefan Reinauer
stepan@coresystems.de for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config MAINBOARD_NAME
+ string
+ default amd/db800
+ depends BOARD_AMD_DB800
+ help
+ This is the default mainboard name.
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ # TODO: Fix PCI ID.
+ default 0x1022
+ depends BOARD_AMD_DB800
+ help
+ Mainboard specific PCI subsystem vendor ID.
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ # TODO: Fix PCI ID.
+ default 0x2323
+ depends BOARD_AMD_DB800
+ help
+ Mainboard specific PCI subsystem device ID.
+
--- /dev/null 2007-09-21 23:50:58.000000000 +0200
+++ LinuxBIOSv3-db800/mainboard/amd/db800/initram.c 2008-03-04 04:02:32.000000000 +0100
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define _MAINOBJECT
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <amd_geodelx.h>
+#include <northbridge/amd/geodelx/raminit.h>
+
+/* #include <device/smbus.h>
+ * TODO: figure out how smbus functions should be done. See smbus_ops.c
+ */
+extern int smbus_read_byte(u16 device, u8 address);
+
+#define MANUALCONF 0 /* Do automatic strapped PLL config */
+#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
+#define PLLMSRLO 0x02000030
+#define DIMM0 ((u8) 0xA0)
+#define DIMM1 ((u8) 0xA2)
+
+u8 spd_read_byte(u16 device, u8 address)
+{
+ u8 spdbyte;
+
+ printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device);
+
+ spdbyte = smbus_read_byte(device, address);
+
+ printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte);
+
+ return spdbyte;
+}
+
+/**
+ * Placeholder in case we ever need it. Since this file is a
+ * template for other motherboards, we want this here and we want the
+ * call in the right place.
+ */
+
+static void mb_gpio_init(void)
+{
+ /* Early mainboard specific GPIO setup */
+}
+
+/**
+ * main for initram for the AMD DB800 development platform.
+ * It might seem that you could somehow do these functions in, e.g., the cpu
+ * code, but the order of operations and what those operations are is VERY
+ * strongly mainboard dependent. It's best to leave it in the mainboard code.
+ */
+int main(void)
+{
+ printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n");
+ post_code(POST_START_OF_MAIN);
+
+ system_preinit();
+ printk(BIOS_DEBUG, "done preinit\n");
+
+ mb_gpio_init();
+ printk(BIOS_DEBUG, "done gpio init\n");
+
+ pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
+ printk(BIOS_DEBUG, "done pll reset\n");
+
+ cpu_reg_init(0, DIMM0, DIMM1);
+ printk(BIOS_DEBUG, "done cpu reg init\n");
+
+ sdram_set_registers();
+ printk(BIOS_DEBUG, "done sdram set registers\n");
+
+ sdram_set_spd_registers(DIMM0, DIMM1);
+ printk(BIOS_DEBUG, "done sdram set spd registers\n");
+
+ sdram_enable(DIMM0, DIMM1);
+ printk(BIOS_DEBUG, "done sdram enable\n");
+
+ /* Check low memory */
+ /*ram_check(0x00000000, 640*1024); */
+
+ printk(BIOS_DEBUG, "stage1 returns\n");
+ return 0;
+}
--- /dev/null 2007-09-21 23:50:58.000000000 +0200
+++ LinuxBIOSv3-db800/mainboard/amd/db800/stage1.c 2008-03-04 03:05:09.000000000 +0100
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <amd_geodelx.h>
+#include <southbridge/amd/cs5536/cs5536.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
+
+#define SERIAL_DEV W83627HF_SP1
+#define SERIAL_IOBASE 0x3f8
+
+void hardware_stage1(void)
+{
+ void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase);
+ post_code(POST_START_OF_MAIN);
+ geodelx_msr_init();
+
+ cs5536_stage1();
+
+ /* NOTE: must do this AFTER the early_setup!
+ * it is counting on some early MSR setup
+ * for cs5536.
+ */
+ cs5536_disable_internal_uart();
+ w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
+
+}
+
+void mainboard_pre_payload(void)
+{
+ geode_pre_payload();
+ banner(BIOS_DEBUG, "mainboard_pre_payload: done");
+}
--- /dev/null 2007-09-21 23:50:58.000000000 +0200
+++ LinuxBIOSv3-db800/mainboard/amd/db800/dts 2008-03-04 04:01:49.000000000 +0100
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Ronald G. Minnich
rminnich@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/{
+ mainboard-vendor = "AMD";
+ mainboard-name = "DB800";
+ cpus { };
+ apic@0 {
+ /config/("northbridge/amd/geodelx/apic");
+ };
+ domain@0 {
+ /config/("northbridge/amd/geodelx/domain");
+ /* Video RAM has to be in 2MB chunks. */
+ geode_video_mb = "8";
+ pci@1,0 {
+ /config/("northbridge/amd/geodelx/pci");
+ };
+ pci@15,0 {
+ /config/("southbridge/amd/cs5536/dts");
+ enable_ide = "1";
+ /* Interrupt enables for LPC bus.
+ * Each bit is an IRQ 0-15. */
+ lpc_serirq_enable = "0x000010da";
+ /* LPC IRQ polarity. Each bit is an IRQ 0-15. */
+ lpc_serirq_polarity = "0x0000EF25";
+ /* 0:continuous 1:quiet */
+ lpc_serirq_mode = "1";
+ /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
+ * See virtual PIC spec. */
+ enable_gpio_int_route = "0x0D0C0700";
+ enable_USBP4_device = "1";
+ };
+ ioport@46 {
+ /config/("superio/winbond/w83627hf/dts");
+ com1enable = "1";
+ };
+ };
+};
--- /dev/null 2007-09-21 23:50:58.000000000 +0200
+++ LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h 2008-03-04 04:02:08.000000000 +0100
@@ -0,0 +1,81 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2007 Advanced Micro Devices, Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <pirq_routing.h>
+
+/* Number of slots and devices in the PIR table */
+#define SLOT_COUNT 4
+
+/* Platform IRQs */
+#define PIRQA 10
+#define PIRQB 11
+#define PIRQC 10
+#define PIRQD 11
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+/*
+ * AMD DB800 interrupt wiring.
+ *
+ * Devices are:
+ *
+ * FIXME
+ *
+ */
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0x00, /* IRQs devoted exclusively to PCI usage */
+ 0x100B, /* Vendor */
+ 0x002B, /* Device */
+ 0, /* Crap (miniport) */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0x00, /* Checksum */
+ {
+ /* If you change the number of entries, change IRQ_SLOT_COUNT above! */
+
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+
+ /* CPU */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+ /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
+ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
+
+ /* On-board ethernet */
+ {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+ /* PCI (slot 1) */
+ {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0},
+ }
+};
--- /dev/null 2007-09-21 23:50:58.000000000 +0200
+++ LinuxBIOSv3-db800/mainboard/amd/db800/cmos.layout 2008-03-04 03:08:52.000000000 +0100
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
--- /dev/null 2007-09-21 23:50:58.000000000 +0200
+++ LinuxBIOSv3-db800/mainboard/amd/db800/Makefile 2008-03-04 03:18:53.000000000 +0100
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006-2007 coresystems GmbH
+## (Written by Stefan Reinauer
stepan@coresystems.de for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
+
+INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+ $(src)/northbridge/amd/geodelx/raminit.c \
+ $(src)/southbridge/amd/cs5536/smbus_initram.c \
+ $(src)/arch/x86/geodelx/geodelx.c
+
+STAGE2_MAINBOARD_OBJ =
+
+$(obj)/coreboot.vpd:
+ $(Q)printf " BUILD DUMMY VPD\n"
+ $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
+
Index: LinuxBIOSv3-db800/mainboard/amd/Kconfig
===================================================================
--- LinuxBIOSv3-db800/mainboard/amd/Kconfig (Revision 630)
+++ LinuxBIOSv3-db800/mainboard/amd/Kconfig (Arbeitskopie)
@@ -23,6 +23,18 @@
prompt "Mainboard model"
depends on VENDOR_AMD
+config BOARD_AMD_DB800
+ bool "DB800"
+ select ARCH_X86
+ select CPU_AMD_GEODELX
+ select OPTION_TABLE
+ select NORTHBRIDGE_AMD_GEODELX
+ select SOUTHBRIDGE_AMD_CS5536
+ select SUPERIO_WINBOND_W83627HF
+ select PIRQ_TABLE
+ help
+ AMD DB800 Geode LX development board.
+
config BOARD_AMD_NORWICH
bool "Norwich"
select ARCH_X86
@@ -36,5 +48,6 @@
endchoice
+source "mainboard/amd/db800/Kconfig"
source "mainboard/amd/norwich/Kconfig"
