YhLu YhLu@tyan.com writes:
Eric,
You overwrite some lines in amd8131....
/* We have to enable MEM and Bus Master for IOAPIC */ value = pci_read_config32(dev, 0x4); value |= 6; pci_write_config32(dev, 0x4, value);
Yep.
But in src/devices/pci_device.c:pci_scan_bus I added: /* Architectural/System devices always need to * be bus masters. */ if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) { dev->command |= PCI_COMMAND_MASTER; }
Which achieves the same thing in a generally less fragile way. We still might have one or two devices that we need to hard code the master command status for but this catches the general case.
Basically system devices have well known interfaces so they are likely to have a generic driver instead of a device specific driver. So enabling them as bus masters looks safe and will fix all of the cases I know about where this is needed.
And I checked and the bus master bit is still getting set on the IOAPICs on the HDAMA.
But thanks good catch, this needed an explanation.
Did I mention I was just a little behind on merging my code? :)
Eric