Re: [coreboot] Use the constant TSC for AMD Family 10h–15h processors?

[Peter Stuge]

Paul Menzel wrote:
> do you know if the timer mentioned in the BIOS and Kernel Developer’s
> Guide (BKGD) for the AMD Family 14h processors [1]
>     2.11.4 BIOS Timer
>
>     The root complex implements a 32-bit microsecond timer (see
>     D0F0xE4_x0130_80F0 and D0F0xE4_x0130_80F1) that the BIOS can use
>     to accurately time wait operations between initialization steps.
>     To ensure that BIOS waits a minimum number of microseconds
>     between steps BIOS should always wait for one microsecond more
>     than the required minimum wait time.
>
> could be used for implementing `tsc_freq_mhz()` as done for Intel
> Haswell processors?

Isn't that quite clear from the text that you quoted?
> Suggestions, if this should be shared and how the files should be
> named are appreciated.

Yes and no. We can do this for coreboot's own code for AMD platforms,
but it obviously does not make much sense to hack this into AGESA if
there are not already provisions for it.

Since AGESA is the only thing relevant going forward the question
is what AGESA needs, timing-wise. Have you checked?

//Peter