Dear coreboot readers!
This is the automated build check service of coreboot.
The developer "linux_junkie" checked in revision 3265 to the coreboot source repository and caused the following changes:
Change Log: Fix so pci device memory allocation does not use memory base address at 0xfec00000, this is reserved for APIC.
Signed-off-by: Aaron Lwe aaron.lwe@gmail.com Acked-by: Joseph Smith joe@settoplinux.org
Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3265&device=serengeti_c...
If something broke during this checkin please be a pain in linux_junkie's neck until the issue is fixed.
If this issue is not fixed within 24h the revision should be backed out.
Best regards, coreboot automatic build system