Miernik wrote:
What I am thinking to do is to put very fast SRAM there (it should work, shouldn't it?),
No, it won't work. SRAM and DRAM operate very differently and have entirely different interfaces. PC chipset memory controllers do not support SRAM.
battery backed up of course, and run the LinuxBIOS and
kernel XiP eXecute in Place (without copying to RAM). Would that work?
No. See answer above.
Imagine I could put 8 MB of fast SRAM there.
Now, would that make sense, is the interface as fast as the FSB if I have a 200 MHz FSB for example?
If I put some SRAM with random access time below 5 ns in there would it communicate with the CPU faster than DRAM in hte DIMM sockets is? Or at least as fast? With the intention of running it XiP.
The memory controllers drive the speed of the memory bus cycles.
Maybe the confusion here is due to an assumption that all memory controllers and memory devices use SPD (or speed detection algorithims) to detect the memory device speeds. SPD is only used with memory modules, not with Flash or SRAM.
Memory devices have timing specifications that guarantee that the memory device will have stable valid data ready to be read from it or that the memory device can write data sent to it AFTER a certain period has elapsed, after the access cycle has been initiated by the memory controller.
-Bari