Stefan Reinauer stepan@suse.de writes:
- Eric W. Biederman ebiederman@lnxi.com [030730 07:55]:
Index: src/southbridge/amd/amd8111/amd8111_ldtstop.c
RCS file: /cvsroot/freebios/freebios2/src/southbridge/amd/amd8111/amd8111_ldtstop.c,v
retrieving revision 1.4 diff -r1.4 amd8111_ldtstop.c 22c22
< pci_write_config16(dev, 0x48, pci_read_config16(dev,0x48) & ~CPUPIN);
pci_write_config32(dev, 0x48, pci_read_config32(dev,0x48) & ~CPUPIN);
The Bios and kernel developers guide specifies 16bit for that register. But since it's all Little Endian it really does not matter.
OTOH, if Tom gets his warm reboot code in place after setting link speed, we can probably get rid of ldtstop assertion completely.
The code is there. There is a challenge because of errata #48 that says the 8131 cannot operate at 800Mhz reliably, but it reports that it can.
How does doing a warm boot there affect boot time?
It pretty much doubles the time before the booloader. And there is the large delay that you see on current Opteron systems.
My plan for today is to see about integrating all of these divergent pieces so I have everything working in one tree.
Eric