Author: stepan Date: 2007-05-10 20:16:03 +0200 (Thu, 10 May 2007) New Revision: 2649
Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/chip.h trunk/LinuxBIOSv2/src/northbridge/amd/lx/grphinit.c trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridge.h trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridgeinit.c trunk/LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.h Log: Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse jordan.crouse@amd.com Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/chip.h 2007-05-10 18:00:24 UTC (rev 2648) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/chip.h 2007-05-10 18:16:03 UTC (rev 2649) @@ -18,8 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-struct northbridge_amd_lx_config -{ +struct northbridge_amd_lx_config {
};
Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/grphinit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/grphinit.c 2007-05-10 18:00:24 UTC (rev 2648) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/grphinit.c 2007-05-10 18:16:03 UTC (rev 2649) @@ -23,42 +23,40 @@ #include <cpu/amd/vr.h> #include <console/console.h>
- /* - * This function mirrors the Graphics_Init routine in GeodeROM. - */ + * This function mirrors the Graphics_Init routine in GeodeROM. + */ void graphics_init(void) { uint16_t wClassIndex, wData, res; - + /* SoftVG initialization */ printk_debug("Graphics init...\n");
/* Call SoftVG with the main configuration parameters. */ /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */ - - wClassIndex = (VRC_VG << 8) + VG_CONFIG; - + + wClassIndex = (VRC_VG << 8) + VG_CONFIG; + /* - * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP) - * External Monochrome Card Support(12) 0, NO - * Controller Priority Select(11) 1, Primary - * Display Select(10:8) 0x0, CRT - * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1, - * defined in mainboard/../Options.lb - * PLL Reference Clock Bypass(0) 0, Default + * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP) + * External Monochrome Card Support(12) 0, NO + * Controller Priority Select(11) 1, Primary + * Display Select(10:8) 0x0, CRT + * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1, + * defined in mainboard/../Options.lb + * PLL Reference Clock Bypass(0) 0, Default */
/* Video RAM has to be given in 2MB chunks * the value is read @ 7:1 (value in 7:0 looks like /2) * so we can add the real value in megabytes */ - - wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK); + + wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | + VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK); vrWrite(wClassIndex, wData); - + res = vrRead(wClassIndex); printk_debug("VRC_VG value: 0x%04x\n", res); } - -
Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c 2007-05-10 18:00:24 UTC (rev 2648) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c 2007-05-10 18:16:03 UTC (rev 2649) @@ -35,12 +35,11 @@ #include "chip.h" #include "northbridge.h"
- /* here is programming for the various MSRs.*/ #define IM_QWAIT 0x100000
-#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */ -#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */ +#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */ +#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */
/* these are the 8-bit attributes for controlling RCONF registers */ #define CACHE_DISABLE (1<<0) @@ -87,33 +86,36 @@ struct msr_defaults { int msr_no; msr_t msr; -} msr_defaults [] = { - {0x1700, {.hi = 0, .lo = IM_QWAIT}}, - {0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES}}, - /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */ - /* for 180a, for now, we assume VSM will configure it */ - /* 180b is left at reset value,a0000-bffff is non-cacheable */ - /* 180c, c0000-dffff is set to write serialize and non-cachable */ - /* oops, 180c will be set by cpu bug handling in cpubug.c */ - //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, - /* 180d is left at default, e0000-fffff is non-cached */ - - /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ - /* we will not set 0x180f, the DMM,yet */ - //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, - //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, - //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, - //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, - /* now for GLPCI routing */ - /* GLIU0 */ - P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80), - P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), - P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), - /* GLIU1 */ - P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80), - P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), - P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), - {0} +} msr_defaults[] = { + { + 0x1700, { + .hi = 0,.lo = IM_QWAIT}}, { + 0x1800, { + .hi = DMCF_WRITE_SERIALIZE_REQUEST,.lo = + DMCF_SERIAL_LOAD_MISSES}}, + /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */ + /* for 180a, for now, we assume VSM will configure it */ + /* 180b is left at reset value,a0000-bffff is non-cacheable */ + /* 180c, c0000-dffff is set to write serialize and non-cachable */ + /* oops, 180c will be set by cpu bug handling in cpubug.c */ + //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, + /* 180d is left at default, e0000-fffff is non-cached */ + /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ + /* we will not set 0x180f, the DMM,yet */ + //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, + //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, + //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, + //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, + /* now for GLPCI routing */ + /* GLIU0 */ + P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80), + P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), + P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), + /* GLIU1 */ + P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80), + P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), + P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), { + 0} };
/* todo: add a resource record. We don't do this here because this may be called when @@ -131,14 +133,14 @@ /* dimm 0 */ dimm = msr.hi; /* installed? */ - if ((dimm & 7) != 7){ + if ((dimm & 7) != 7) { sizem = 4 << ((dimm >> 12) & 0x0F); }
- /* dimm 1*/ + /* dimm 1 */ dimm = msr.hi >> 16; /* installed? */ - if ((dimm & 7) != 7){ + if ((dimm & 7) != 7) { sizem += 4 << ((dimm >> 12) & 0x0F); }
@@ -146,27 +148,24 @@ return sizem; }
- - static void enable_shadow(device_t dev) { }
-static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { //msr_t msr;
printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__); - + enable_shadow(dev); /* * Swiss cheese */ //msr = rdmsr(MSR_GLIU0_SHADOW); - + //msr.hi |= 0x3; //msr.lo |= 0x30000; -
//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo); //printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo); @@ -180,19 +179,20 @@
last = &dev->resource[dev->resources];
- for(resource = &dev->resource[0]; resource < last; resource++) - { + for (resource = &dev->resource[0]; resource < last; resource++) {
// andrei: do not change the base address, it will make the VSA virtual registers unusable //pci_set_resource(dev, resource); // FIXME: static allocation may conflict with dynamic mappings! }
- for(link = 0; link < dev->links; link++) { + for (link = 0; link < dev->links; link++) { struct bus *bus; bus = &dev->link[link]; if (bus->children) { - printk_debug("my_dev_set_resources: assign_resources %d\n", bus); + printk_debug + ("my_dev_set_resources: assign_resources %d\n", + bus); assign_resources(bus); } } @@ -210,18 +210,18 @@ if (line) { pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); } - + /* set the cache line size, so far 64 bytes is good for everyone */ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); }
static struct device_operations northbridge_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = northbridge_set_resources, + .read_resources = pci_dev_read_resources, + .set_resources = northbridge_set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, };
static struct pci_driver northbridge_driver __pci_driver = { @@ -230,35 +230,37 @@ .device = PCI_DEVICE_ID_AMD_LXBRIDGE, };
- static void pci_domain_read_resources(device_t dev) { - struct resource *resource; + struct resource *resource; printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
- /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + resource->limit = 0xffffUL; + resource->flags = + IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
- /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + resource->limit = 0xffffffffULL; + resource->flags = + IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; }
static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) + unsigned long basek, unsigned long sizek) { - struct resource *resource; + struct resource *resource;
- if (!sizek) return; - - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + if (!sizek) + return; + + resource = new_resource(dev, index); + resource->base = ((resource_t) basek) << 10; + resource->size = ((resource_t) sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; }
static void pci_domain_set_resources(device_t dev) @@ -269,12 +271,11 @@ printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
mc_dev = dev->link[0].children; - if (mc_dev) - { + if (mc_dev) { /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 1024, (get_systop()- 0x100000)/1024 ); // Systop - 1 MB -> KB + ram_resource(dev, idx++, 1024, (get_systop() - 0x100000) / 1024); // Systop - 1 MB -> KB }
assign_resources(&dev->link[0]); @@ -295,8 +296,8 @@ printk_debug("Before VSA:\n"); // print_conf();
- do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;) - + do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;) + printk_debug("After VSA:\n"); // print_conf();
@@ -308,23 +309,23 @@ { printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + return max; }
static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = enable_childrens_resources, - .scan_bus = pci_domain_scan_bus, - .enable = pci_domain_enable, -}; + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = enable_childrens_resources, + .scan_bus = pci_domain_scan_bus, + .enable = pci_domain_enable, +};
static void cpu_bus_init(device_t dev) { printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
- initialize_cpus(&dev->link[0]); + initialize_cpus(&dev->link[0]); }
static void cpu_bus_noop(device_t dev) @@ -332,26 +333,26 @@ }
static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(struct device *dev) { - printk_spew(">> Entering northbridge.c: %s with path %d\n", - __FUNCTION__, dev->path.type); + printk_spew(">> Entering northbridge.c: %s with path %d\n", + __FUNCTION__, dev->path.type);
- /* Set the operations if it is a special bus type */ + /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) dev->ops = &pci_domain_ops; else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) - dev->ops = &cpu_bus_ops; + dev->ops = &cpu_bus_ops; }
struct chip_operations northbridge_amd_lx_ops = { CHIP_NAME("AMD LX Northbridge") - .enable_dev = enable_dev, + .enable_dev = enable_dev, };
Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridge.h =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridge.h 2007-05-10 18:00:24 UTC (rev 2648) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridge.h 2007-05-10 18:16:03 UTC (rev 2649) @@ -24,4 +24,4 @@ extern unsigned int lx_scan_root_bus(device_t root, unsigned int max); int sizeram(void);
-#endif /* NORTHBRIDGE_AMD_LX_H */ +#endif /* NORTHBRIDGE_AMD_LX_H */
Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridgeinit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridgeinit.c 2007-05-10 18:00:24 UTC (rev 2648) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridgeinit.c 2007-05-10 18:16:03 UTC (rev 2649) @@ -33,7 +33,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/cache.h>
- struct gliutable { unsigned long desc_name; unsigned short desc_type; @@ -41,85 +40,85 @@ };
struct gliutable gliu0table[] = { - {.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/ - {.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc*/ - {.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/ - {.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/ - {.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/ - {.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, - {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, + {.desc_name = MSR_GLIU0_BASE1,.desc_type = BM,.hi = MSR_MC + 0x0,.lo = 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name = MSR_GLIU0_BASE2,.desc_type = BM,.hi = MSR_MC + 0x0,.lo = (0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ + {.desc_name = MSR_GLIU0_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_MC + 0x0,.lo = 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ + {.desc_name = MSR_GLIU0_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_MC,.lo = 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = MSR_GLIU0_SMM,.desc_type = BMO_SMM,.hi = MSR_MC,.lo = 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo = + GL0_CPU}, + {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0}, };
- struct gliutable gliu1table[] = { - {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/ - {.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc*/ - {.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode)*/ - {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/ - {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/ - {.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, - {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0*/ - {.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0}, + {.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = (0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ + {.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_GL0 + 0x0,.lo = 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ + {.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo = + GL1_GLIU0}, + {.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO,.hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0}, /* FooGlue FPU 0xF0 */ + {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0}, };
-struct gliutable *gliutables[] = {gliu0table, gliu1table, 0}; +struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
struct msrinit { unsigned long msrnum; msr_t msr; };
-struct msrinit ClockGatingDefault [] = { - {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, - {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0555}}, - {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0014}}, - {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {VIP_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - {AES_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {CPU_BC_PMODE_MSR, {.hi=0x00,.lo=0x70303}}, - {0xffffffff, {0xffffffff, 0xffffffff}}, +struct msrinit ClockGatingDefault[] = { + {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, + {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, + {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, + {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0555}}, + {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, + {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0014}}, + {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {VIP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, + {AES_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {CPU_BC_PMODE_MSR, {.hi = 0x00,.lo = 0x70303}}, + {0xffffffff, {0xffffffff, 0xffffffff}}, };
/* */ /* SET GeodeLink PRIORITY*/ /* */ -struct msrinit GeodeLinkPriorityTable [] = { - {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, - {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, - {VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, - {GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, - {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0017}}, - {GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, - {VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, - {AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, - {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END*/ +struct msrinit GeodeLinkPriorityTable[] = { + {CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}}, + {DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}}, + {VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}}, + {GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}}, + {GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0017}}, + {GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}}, + {VIP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}}, + {AES_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0013}}, + {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */ };
extern int sizeram(void);
-static void -writeglmsr(struct gliutable *gl){ +static void writeglmsr(struct gliutable *gl) +{ msr_t msr;
msr.lo = gl->lo; msr.hi = gl->hi; wrmsr(gl->desc_name, msr); // MSR - see table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); // GX3 + printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); // GX3 }
-static void -ShadowInit(struct gliutable *gl) +static void ShadowInit(struct gliutable *gl) { msr_t msr;
msr = rdmsr(gl->desc_name);
if (msr.lo == 0) { - writeglmsr(gl); + writeglmsr(gl); } }
@@ -129,8 +128,8 @@ msr_t msr; int sizembytes, sizebytes;
- /* - * Figure out how much RAM is in the machine and alocate all to the + /* + * Figure out how much RAM is in the machine and alocate all to the * system. We will adjust for SMM now and Frame Buffer later. */ sizembytes = sizeram(); @@ -141,25 +140,26 @@ printk_debug("usable RAM: %d bytes\n", sizebytes);
/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo - The top 8 bits go into 0-7 of msr.hi. */ + The top 8 bits go into 0-7 of msr.hi. */ sizebytes--; msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24); - sizebytes <<= 8; /* move bits 23:12 in bits 31:20. */ + sizebytes <<= 8; /* move bits 23:12 in bits 31:20. */ sizebytes &= 0xfff00000; - sizebytes |= 0x100; /* start at 1MB */ + sizebytes |= 0x100; /* start at 1MB */ msr.lo = sizebytes;
wrmsr(gl->desc_name, msr); // MSR - see table above printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, - gl->desc_name, msr.hi, msr.lo); + gl->desc_name, msr.hi, msr.lo); }
-static void SMMGL0Init(struct gliutable *gl) { +static void SMMGL0Init(struct gliutable *gl) +{ msr_t msr; - int sizebytes = sizeram()<<20; + int sizebytes = sizeram() << 20; long offset;
- sizebytes -= (SMM_SIZE*1024); + sizebytes -= (SMM_SIZE * 1024);
printk_debug("%s: %d bytes\n", __FUNCTION__, sizebytes);
@@ -169,51 +169,55 @@ printk_debug("%s: offset is 0x%08x\n", __FUNCTION__, SMM_OFFSET);
msr.hi = offset << 8 | gl->hi; - msr.hi |= SMM_OFFSET>>24; + msr.hi |= SMM_OFFSET >> 24;
msr.lo = SMM_OFFSET << 8; - msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; - + msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff; + wrmsr(gl->desc_name, msr); // MSR - See table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); + printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, + gl->desc_name, msr.hi, msr.lo); }
-static void SMMGL1Init(struct gliutable *gl) { +static void SMMGL1Init(struct gliutable *gl) +{ msr_t msr; - printk_debug("%s:\n", __FUNCTION__ ); + printk_debug("%s:\n", __FUNCTION__);
msr.hi = gl->hi; /* I don't think this is needed */ msr.hi &= 0xffffff00; msr.hi |= (SMM_OFFSET >> 24); msr.lo = (SMM_OFFSET << 8) & 0xFFF00000; - msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; - + msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff; + wrmsr(gl->desc_name, msr); // MSR - See table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); + printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, + gl->desc_name, msr.hi, msr.lo); }
-static void GLIUInit(struct gliutable *gl){ +static void GLIUInit(struct gliutable *gl) +{
- while (gl->desc_type != GL_END){ - switch(gl->desc_type){ - default: + while (gl->desc_type != GL_END) { + switch (gl->desc_type) { + default: /* For Unknown types: Write then read MSR */ writeglmsr(gl); - case SC_SHADOW: /* Check for a Shadow entry*/ + case SC_SHADOW: /* Check for a Shadow entry */ ShadowInit(gl); break; - - case R_SYSMEM: /* check for a SYSMEM entry*/ + + case R_SYSMEM: /* check for a SYSMEM entry */ SysmemInit(gl); break; - - case BMO_SMM : /* check for a SMM entry*/ + + case BMO_SMM: /* check for a SMM entry */ SMMGL0Init(gl); break; - - case BM_SMM : /* check for a SMM entry*/ - SMMGL1Init(gl); + + case BM_SMM: /* check for a SMM entry */ + SMMGL1Init(gl); break; } gl++; @@ -221,23 +225,24 @@
}
- /* ***************************************************************************/ - /* **/ - /* * GLPCIInit*/ - /* **/ - /* * Set up GLPCI settings for reads/write into memory*/ - /* * R0: 0-640KB,*/ - /* * R1: 1MB - Top of System Memory*/ - /* * R2: SMM Memory*/ - /* * R3: Framebuffer? - not set up yet*/ - /* * R4: ??*/ - /* **/ - /* * Entry:*/ - /* * Exit:*/ - /* * Modified:*/ - /* **/ - /* ***************************************************************************/ -static void GLPCIInit(void){ + /* ************************************************************************** */ + /* * */ + /* * GLPCIInit */ + /* * */ + /* * Set up GLPCI settings for reads/write into memory */ + /* * R0: 0-640KB, */ + /* * R1: 1MB - Top of System Memory */ + /* * R2: SMM Memory */ + /* * R3: Framebuffer? - not set up yet */ + /* * R4: ?? */ + /* * */ + /* * Entry: */ + /* * Exit: */ + /* * Modified: */ + /* * */ + /* ************************************************************************** */ +static void GLPCIInit(void) +{ struct gliutable *gl = 0; int i; msr_t msr; @@ -245,19 +250,21 @@ int nic_grants_control, enable_bus_parking;
/* */ - /* R0 - GLPCI settings for Conventional Memory space.*/ + /* R0 - GLPCI settings for Conventional Memory space. */ /* */ - msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */ - msr.lo = 0; /* 0*/ - msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET; + msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */ + msr.lo = 0; /* 0 */ + msr.lo |= + GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET + + GLPCI_RC_LOWER_WC_SET; msrnum = GLPCI_RC0; wrmsr(msrnum, msr);
/* */ - /* R1 - GLPCI settings for SysMem space.*/ + /* R1 - GLPCI settings for SysMem space. */ /* */ - /* Get systop from GLIU0 SYSTOP Descriptor*/ - for(i = 0; gliu0table[i].desc_name != GL_END; i++) { + /* Get systop from GLIU0 SYSTOP Descriptor */ + for (i = 0; gliu0table[i].desc_name != GL_END; i++) { if (gliu0table[i].desc_type == R_SYSMEM) { gl = &gliu0table[i]; break; @@ -268,8 +275,8 @@ msrnum = gl->desc_name; msr = rdmsr(msrnum); /* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00 - * translates to a base of 0x00100000 and top of 0xffbf0000 - * base of 1M and top of around 256M + * translates to a base of 0x00100000 and top of 0xffbf0000 + * base of 1M and top of around 256M */ /* we have to create a page-aligned (4KB page) address for base and top */ /* So we need a high page aligned addresss (pah) and low page aligned address (pal) @@ -280,28 +287,34 @@ pah <<= 12;
pal = msr.lo << 12; - msr.hi = pah; - msr.lo = pal; - msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET; - printk_debug("GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); + msr.hi = pah; + msr.lo = pal; + msr.lo |= + GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | + GLPCI_RC_LOWER_WC_SET; + printk_debug("GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", + msr.lo, msr.hi); msrnum = GLPCI_RC1; wrmsr(msrnum, msr); }
/* */ - /* R2 - GLPCI settings for SMM space */ + /* R2 - GLPCI settings for SMM space */ /* */ - msr.hi = ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; - msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT; + msr.hi = + ((SMM_OFFSET + + (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; + msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT; msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET; - printk_debug("GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); + printk_debug("GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, + msr.hi); msrnum = GLPCI_RC2; wrmsr(msrnum, msr);
/* this is done elsewhere already, but it does no harm to do it more than once */ - /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/ - msr.lo = 0x021212121; /* cache disabled and write serialized */ - msr.hi = 0x021212121; /* cache disabled and write serialized */ + /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */ + msr.lo = 0x021212121; /* cache disabled and write serialized */ + msr.hi = 0x021212121; /* cache disabled and write serialized */
msrnum = CPU_RCONF_A0_BF; wrmsr(msrnum, msr); @@ -312,181 +325,186 @@ msrnum = CPU_RCONF_E0_FF; wrmsr(msrnum, msr);
- /* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup.*/ + /* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */ msrnum = GLPCI_A0_BF; - msr.hi = 0x35353535; - msr.lo = 0x35353535; + msr.hi = 0x35353535; + msr.lo = 0x35353535; wrmsr(msrnum, msr);
msrnum = GLPCI_C0_DF; - msr.hi = 0x35353535; - msr.lo = 0x35353535; + msr.hi = 0x35353535; + msr.lo = 0x35353535; wrmsr(msrnum, msr);
msrnum = GLPCI_E0_FF; - msr.hi = 0x35353535; - msr.lo = 0x35353535; + msr.hi = 0x35353535; + msr.lo = 0x35353535; wrmsr(msrnum, msr);
- /* Set WSREQ*/ + /* Set WSREQ */ msrnum = CPU_DM_CONFIG0; msr = rdmsr(msrnum); - msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT); + msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT); msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT; /* reduce to 1 for safe mode */ wrmsr(msrnum, msr);
/* we are ignoring the 5530 case for now, and perhaps forever. */
/* */ - /* 553x NB Init*/ - /* */ + /* 553x NB Init */ + /* */
/* Arbiter setup */ - enable_preempt = GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET | GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET; + enable_preempt = + GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET | + GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET; enable_cpu_override = GLPCI_ARB_LOWER_COV_SET; enable_bus_parking = GLPCI_ARB_LOWER_PARK_SET; - nic_grants_control = (0x4 << GLPCI_ARB_UPPER_R2_SHIFT) | (0x3 << GLPCI_ARB_UPPER_H2_SHIFT ); + nic_grants_control = + (0x4 << GLPCI_ARB_UPPER_R2_SHIFT) | (0x3 << + GLPCI_ARB_UPPER_H2_SHIFT);
msrnum = GLPCI_ARB; msr = rdmsr(msrnum);
- msr.hi |= nic_grants_control; - msr.lo |= enable_cpu_override | enable_preempt | enable_bus_parking; + msr.hi |= nic_grants_control; + msr.lo |= enable_cpu_override | enable_preempt | enable_bus_parking; wrmsr(msrnum, msr);
msrnum = GLPCI_CTRL; msr = rdmsr(msrnum);
- msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .)*/ - msr.lo |= GLPCI_CTRL_LOWER_LDE_SET; + msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */ + msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;
- msr.lo &= ~ (0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT); - msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT; + msr.lo &= ~(0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT); + msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;
- msr.lo &= ~ (0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT); - msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT; - - msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT); - msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT; - - msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT); - msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT; - - msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT); - msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT; - - msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT); - msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT; - - msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT); - msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT; + msr.lo &= ~(0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT); + msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT; + + msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT); + msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT; + + msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT); + msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT; + + msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT); + msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT; + + msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT); + msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT; + + msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT); + msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT; wrmsr(msrnum, msr);
- /* Set GLPCI Latency Timer */ msrnum = GLPCI_CTRL; msr = rdmsr(msrnum); - msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone */ + msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone */ wrmsr(msrnum, msr);
- /* GLPCI_SPARE*/ + /* GLPCI_SPARE */ msrnum = GLPCI_SPARE; msr = rdmsr(msrnum); - msr.lo &= ~ 0x7; - msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET; + msr.lo &= ~0x7; + msr.lo |= + GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | + GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | + GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET; wrmsr(msrnum, msr); }
- - - /* ***************************************************************************/ - /* **/ - /* * ClockGatingInit*/ - /* **/ - /* * Enable Clock Gating.*/ - /* **/ - /* * Entry:*/ - /* * Exit:*/ - /* * Modified:*/ - /* **/ - /* ***************************************************************************/ -static void ClockGatingInit (void){ + /* ************************************************************************** */ + /* * */ + /* * ClockGatingInit */ + /* * */ + /* * Enable Clock Gating. */ + /* * */ + /* * Entry: */ + /* * Exit: */ + /* * Modified: */ + /* * */ + /* ************************************************************************** */ +static void ClockGatingInit(void) +{ msr_t msr; struct msrinit *gating = ClockGatingDefault; int i;
- for(i = 0; gating->msrnum != 0xffffffff; i++) { + for (i = 0; gating->msrnum != 0xffffffff; i++) { msr = rdmsr(gating->msrnum); msr.hi |= gating->msr.hi; msr.lo |= gating->msr.lo; - /* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, - gating->msrnum, msr.hi, msr.lo); */ // GX3 + /* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, + gating->msrnum, msr.hi, msr.lo); */// GX3 wrmsr(gating->msrnum, msr); // MSR - See the table above - gating +=1; + gating += 1; }
}
-static void GeodeLinkPriority(void){ +static void GeodeLinkPriority(void) +{ msr_t msr; struct msrinit *prio = GeodeLinkPriorityTable; int i;
- for(i = 0; prio->msrnum != 0xffffffff; i++) { + for (i = 0; prio->msrnum != 0xffffffff; i++) { msr = rdmsr(prio->msrnum); msr.hi |= prio->msr.hi; msr.lo &= ~0xfff; msr.lo |= prio->msr.lo; - /* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, - prio->msrnum, msr.hi, msr.lo); */ // GX3 + /* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, + prio->msrnum, msr.hi, msr.lo); */// GX3 wrmsr(prio->msrnum, msr); // MSR - See the table above - prio +=1; + prio += 1; } }
- - /* * Get the GLIU0 shadow register settings * If the setShadow function is used then all shadow descriptors * will stay sync'ed. */ -static uint64_t getShadow(void){ +static uint64_t getShadow(void) +{ msr_t msr;
msr = rdmsr(MSR_GLIU0_SHADOW); - return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; + return (((uint64_t) msr.hi) << 32) | msr.lo; }
- /* * Set the cache RConf registers for the memory hole. * Keeps all cache shadow descriptors sync'ed. * This is part of the PCI lockup solution * Entry: EDX:EAX is the shadow settings */ -static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo){ +static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) +{
// ok this is whacky bit translation time. int bit; uint8_t shadowByte; - msr_t msr = {0, 0}; + msr_t msr = { 0, 0 }; shadowByte = (uint8_t) (shadowLo >> 16);
// load up D000 settings in edx. for (bit = 8; (bit > 4); bit--) { msr.hi <<= 8; - msr.hi |= 1; // cache disable PCI/Shadow memory + msr.hi |= 1; // cache disable PCI/Shadow memory if (shadowByte && (1 << bit)) - msr.hi |= 0x20; // write serialize PCI memory + msr.hi |= 0x20; // write serialize PCI memory }
// load up C000 settings in eax. - for ( ; bit; bit--) { + for (; bit; bit--) { msr.lo <<= 8; - msr.lo |= 1; // cache disable PCI/Shadow memory + msr.lo |= 1; // cache disable PCI/Shadow memory if (shadowByte && (1 << bit)) - msr.lo |= 0x20; // write serialize PCI memory + msr.lo |= 0x20; // write serialize PCI memory }
wrmsr(CPU_RCONF_C0_DF, msr); @@ -496,23 +514,22 @@ // load up F000 settings in edx. for (bit = 8; (bit > 4); bit--) { msr.hi <<= 8; - msr.hi |= 1; // cache disable PCI/Shadow memory + msr.hi |= 1; // cache disable PCI/Shadow memory if (shadowByte && (1 << bit)) - msr.hi |= 0x20; // write serialize PCI memory + msr.hi |= 0x20; // write serialize PCI memory }
// load up E000 settings in eax. - for ( ; bit; bit--) { + for (; bit; bit--) { msr.lo <<= 8; - msr.lo |= 1; // cache disable PCI/Shadow memory + msr.lo |= 1; // cache disable PCI/Shadow memory if (shadowByte && (1 << bit)) - msr.lo |= 0x20; // write serialize PCI memory + msr.lo |= 0x20; // write serialize PCI memory }
wrmsr(CPU_RCONF_E0_FF, msr); }
- /* * Set the GLPCI registers for the memory hole. * Keeps all cache shadow descriptors sync'ed. @@ -521,15 +538,14 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo) { msr_t msr; - + // Set the Enable Register. msr = rdmsr(GLPCI_REN); msr.lo &= 0xFFFF00FF; - msr.lo |= ( (shadowLo & 0xFFFF0000) >> 8); + msr.lo |= ((shadowLo & 0xFFFF0000) >> 8); wrmsr(GLPCI_REN, msr); }
- /* * Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW. * Keeps all shadow descriptors sync'ed. @@ -539,7 +555,7 @@ { int i; msr_t msr; - struct gliutable* pTable; + struct gliutable *pTable; uint32_t shadowLo, shadowHi;
shadowLo = (uint32_t) shadowSettings; @@ -548,21 +564,25 @@ setShadowRCONF(shadowHi, shadowLo); setShadowGLPCI(shadowHi, shadowLo);
- for(i = 0; gliutables[i]; i++) { - for (pTable = gliutables[i]; pTable->desc_type != GL_END; pTable++) { + for (i = 0; gliutables[i]; i++) { + for (pTable = gliutables[i]; pTable->desc_type != GL_END; + pTable++) { if (pTable->desc_type == SC_SHADOW) {
msr = rdmsr(pTable->desc_name); msr.lo = (uint32_t) shadowSettings; - msr.hi &= 0xFFFF0000; // maintain PDID in upper EDX - msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF; + msr.hi &= 0xFFFF0000; // maintain PDID in upper EDX + msr.hi |= + ((uint32_t) (shadowSettings >> 32)) & + 0x0000FFFF; wrmsr(pTable->desc_name, msr); // MSR - See the table above } } } }
-static void rom_shadow_settings(void){ +static void rom_shadow_settings(void) +{
uint64_t shadowSettings = getShadow(); shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes @@ -571,8 +591,6 @@ setShadow(shadowSettings); }
- - /*************************************************************************** * * L1Init @@ -583,7 +601,7 @@ * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * SYSTOP(27:8) = top of system memory - * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough + * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough * ***************************************************************************/ #define SYSMEM_RCONF_WRITETHROUGH 8 @@ -599,27 +617,26 @@ uint8_t SysMemCacheProp;
/* Locate SYSMEM entry in GLIU0table */ - for(i = 0; gliu0table[i].desc_name != GL_END; i++) { + for (i = 0; gliu0table[i].desc_name != GL_END; i++) { if (gliu0table[i].desc_type == R_SYSMEM) { gl = &gliu0table[i]; break; } } if (gl == 0) { - post_code(0xCE); /* POST_RCONFInitError */ - while (1); + post_code(0xCE); /* POST_RCONFInitError */ + while (1) ; } - -// sysdescfound: +// sysdescfound: msr = rdmsr(gl->desc_name);
- /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the - * top 8 bits go into 0-7 of edx. + /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the + * top 8 bits go into 0-7 of edx. */ msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF); msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF; msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; // 8 - + // Set Default SYSMEM region properties msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; // NOT writethrough == writeback 8 (or ~8)
@@ -628,27 +645,32 @@ msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
// Set the ROMBASE. This is usually FFFC0000h - msr.hi |= (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT; + msr.hi |= + (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;
// Set ROMBASE cache properties. msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24)); - + // now program RCONF_DEFAULT wrmsr(CPU_RCONF_DEFAULT, msr); - printk_debug("CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n",msr.hi,msr.lo); + printk_debug("CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi, + msr.lo);
// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties. // Set to match system memory cache properties. msr = rdmsr(CPU_RCONF_DEFAULT); SysMemCacheProp = (uint8_t) (msr.lo & 0xFF); msr = rdmsr(CPU_RCONF_BYPASS); - msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp; + msr.lo = + (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp; wrmsr(CPU_RCONF_BYPASS, msr); - - printk_debug("CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi, msr.lo); + + printk_debug("CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi, + msr.lo); }
-static void enable_L2_cache(void) { +static void enable_L2_cache(void) +{ msr_t msr;
/* Instruction Memory Configuration register @@ -695,13 +717,14 @@ wbinvd(); }
-uint32_t get_systop(void) { +uint32_t get_systop(void) +{ struct gliutable *gl = 0; uint32_t systop; msr_t msr; int i;
- for(i = 0; gliu0table[i].desc_name != GL_END; i++) { + for (i = 0; gliu0table[i].desc_name != GL_END; i++) { if (gliu0table[i].desc_type == R_SYSMEM) { gl = &gliu0table[i]; break; @@ -710,9 +733,10 @@ if (gl) { msr = rdmsr(gl->desc_name); systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8); - systop += 0x1000; /* 4K */ - }else{ - systop = ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024; + systop += 0x1000; /* 4K */ + } else { + systop = + ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024; } return systop; } @@ -729,12 +753,12 @@ int i; printk_debug("Enter %s\n", __FUNCTION__);
- for(i = 0; gliutables[i]; i++) + for (i = 0; gliutables[i]; i++) GLIUInit(gliutables[i]);
- /* Now that the descriptor to memory is set up.*/ - /* The memory controller needs one read to synch its lines before it can be used.*/ - i = *(int *) 0; + /* Now that the descriptor to memory is set up. */ + /* The memory controller needs one read to synch its lines before it can be used. */ + i = *(int *)0;
GeodeLinkPriority();
@@ -749,4 +773,3 @@ __asm__ __volatile__("FINIT\n"); printk_debug("Exit %s\n", __FUNCTION__); } -
Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c 2007-05-10 18:00:24 UTC (rev 2648) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c 2007-05-10 18:16:03 UTC (rev 2649) @@ -22,43 +22,47 @@ { msr_t msrGlcpSysRstpll;
- msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL); - + msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL); + print_debug("_MSR GLCP_SYS_RSTPLL ("); - print_debug_hex32(GLCP_SYS_RSTPLL); - print_debug(") value is: "); - print_debug_hex32(msrGlcpSysRstpll.hi); - print_debug(":"); - print_debug_hex32(msrGlcpSysRstpll.lo); - print_debug("\r\n"); + print_debug_hex32(GLCP_SYS_RSTPLL); + print_debug(") value is: "); + print_debug_hex32(msrGlcpSysRstpll.hi); + print_debug(":"); + print_debug_hex32(msrGlcpSysRstpll.lo); + print_debug("\r\n"); POST_CODE(POST_PLL_INIT); - - if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))){ + + if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { print_debug("Configuring PLL\n"); - if(manualconf){ + if (manualconf) { POST_CODE(POST_PLL_MANUAL); /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ - msrGlcpSysRstpll.hi = PLLMSRhi; + msrGlcpSysRstpll.hi = PLLMSRhi;
/* Hold Count - how long we will sit in reset */ - msrGlcpSysRstpll.lo = PLLMSRlo; - } - else{ - /*automatic configuration (straps)*/ + msrGlcpSysRstpll.lo = PLLMSRlo; + } else { + /*automatic configuration (straps) */ POST_CODE(POST_PLL_STRAP); - msrGlcpSysRstpll.lo &= ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT); - msrGlcpSysRstpll.lo |= (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT); - msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_COREBYPASS_SET | RSTPPL_LOWER_MBBYPASS_SET); - msrGlcpSysRstpll.lo |= RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET; + msrGlcpSysRstpll.lo &= + ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT); + msrGlcpSysRstpll.lo |= + (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT); + msrGlcpSysRstpll.lo &= + ~(RSTPPL_LOWER_COREBYPASS_SET | + RSTPPL_LOWER_MBBYPASS_SET); + msrGlcpSysRstpll.lo |= + RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET; } - /* Use SWFLAGS to remember: "we've already been here" */ + /* Use SWFLAGS to remember: "we've already been here" */ msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
- /* "reset the chip" value */ + /* "reset the chip" value */ msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- /* You should never get here..... The chip has reset.*/ + /* You should never get here..... The chip has reset. */ print_debug("CONFIGURING PLL FAILURE\n"); POST_CODE(POST_PLL_RESET_FAIL); __asm__ __volatile__("hlt\n"); @@ -68,37 +72,38 @@ return; }
-static unsigned int CPUSpeed(void){ +static unsigned int CPUSpeed(void) +{ unsigned int speed; msr_t msr;
msr = rdmsr(GLCP_SYS_RSTPLL); - speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F)+1)*333)/10; - if((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F)+1)*333)%10) > 5){ + speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10; + if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) { ++speed; } - return(speed); + return (speed); } -static unsigned int GeodeLinkSpeed(void){ +static unsigned int GeodeLinkSpeed(void) +{ unsigned int speed; msr_t msr;
msr = rdmsr(GLCP_SYS_RSTPLL); - speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F)+1)*333)/10; - if((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F)+1)*333)%10) > 5){ + speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10; + if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) { ++speed; } - return(speed); + return (speed); } -static unsigned int PCISpeed(void){ +static unsigned int PCISpeed(void) +{ msr_t msr;
msr = rdmsr(GLCP_SYS_RSTPLL); - if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)){ - return(66); + if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) { + return (66); + } else { + return (33); } - else{ - return(33); - } } -
Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2007-05-10 18:00:24 UTC (rev 2648) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2007-05-10 18:16:03 UTC (rev 2649) @@ -22,9 +22,13 @@ #include <spd.h> #include "southbridge/amd/cs5536/cs5536.h"
-static const unsigned char NumColAddr[] = {0x00,0x10,0x11,0x00,0x00,0x00,0x00,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F}; +static const unsigned char NumColAddr[] = { + 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F +};
-static void auto_size_dimm(unsigned int dimm){ +static void auto_size_dimm(unsigned int dimm) +{ uint32_t dimm_setting; uint16_t dimm_size; uint8_t spd_byte; @@ -33,60 +37,58 @@ dimm_setting = 0;
/* Check that we have a dimm */ - if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF){ + if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) { return; -} + }
/* Field: Module Banks per DIMM */ /* EEPROM byte usage: (5) Number of DIMM Banks */ spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS); - if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)){ + if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) { print_debug("Number of module banks not compatible\r\n"); POST_CODE(ERROR_BANK_SET); __asm__ __volatile__("hlt\n"); } dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
- /* Field: Banks per SDRAM device */ /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */ spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); - if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)){ + if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) { print_debug("Number of device banks not compatible\r\n"); POST_CODE(ERROR_BANK_SET); __asm__ __volatile__("hlt\n"); } dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
- /*; Field: DIMM size - *; EEPROM byte usage: (3) Number or Row Addresses - *; (4) Number of Column Addresses - *; (5) Number of DIMM Banks - *; (31) Module Bank Density - *; Size = Module Density * Module Banks + *; EEPROM byte usage: (3) Number or Row Addresses + *; (4) Number of Column Addresses + *; (5) Number of DIMM Banks + *; (31) Module Bank Density + *; Size = Module Density * Module Banks */ - if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)){ + if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) + || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) { print_debug("Assymetirc DIMM not compatible\r\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); __asm__ __volatile__("hlt\n"); }
dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY); - dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out*/ - dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top*/ + dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */ + dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
- /* Module Density * Module Banks */ - dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ + /* Module Density * Module Banks */ + dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ dimm_size = __builtin_ctz(dimm_size); - if (dimm_size > 8){ /* 8 is 1GB only support 1GB per DIMM */ + if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */ print_debug("Only support up to 1 GB per DIMM\r\n"); POST_CODE(ERROR_DENSITY_DIMM); __asm__ __volatile__("hlt\n"); } dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
- /*; Field: PAGE size *; EEPROM byte usage: (4) Number of Column Addresses *; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM) @@ -116,98 +118,98 @@ POST_CODE(ERROR_SET_PAGE); __asm__ __volatile__("hlt\n"); } - spd_byte -=7; - if (spd_byte > 5){ /* if the value is above 6 it means >12 address lines */ - spd_byte = 7; /* which means >32k so set to disabled */ + spd_byte -= 7; + if (spd_byte > 5) { /* if the value is above 6 it means >12 address lines */ + spd_byte = 7; /* which means >32k so set to disabled */ } - dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */ + dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
msr = rdmsr(MC_CF07_DATA); - if (dimm == DIMM0){ + if (dimm == DIMM0) { msr.hi &= 0xFFFF0000; msr.hi |= dimm_setting; - }else{ + } else { msr.hi &= 0x0000FFFF; msr.hi |= dimm_setting << 16; } wrmsr(MC_CF07_DATA, msr); }
- -static void checkDDRMax(void){ +static void checkDDRMax(void) +{ uint8_t spd_byte0, spd_byte1; uint16_t speed;
- /* PC133 identifier */ + /* PC133 identifier */ spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; }
/* I don't think you need this check. - if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){ - print_debug("DIMM overclocked. Check GeodeLink Speed\r\n"); - POST_CODE(POST_PLL_MEM_FAIL); - __asm__ __volatile__("hlt\n"); - }*/ + if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){ + print_debug("DIMM overclocked. Check GeodeLink Speed\r\n"); + POST_CODE(POST_PLL_MEM_FAIL); + __asm__ __volatile__("hlt\n"); + } */
- /* Use the slowest DIMM */ - if (spd_byte0 < spd_byte1){ + if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; }
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - speed = 2*((10000/(((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)))); + speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F))));
/* current speed > max speed? */ - if (GeodeLinkSpeed() > speed){ + if (GeodeLinkSpeed() > speed) { print_debug("DIMM overclocked. Check GeodeLink Speed\r\n"); POST_CODE(POST_PLL_MEM_FAIL); __asm__ __volatile__("hlt\n"); } }
+const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
-const uint16_t REF_RATE[] = {15, 3, 7, 31, 62, 125}; /* ns */ - -static void set_refresh_rate(void){ +static void set_refresh_rate(void) +{ uint8_t spd_byte0, spd_byte1; uint16_t rate0, rate1; msr_t msr;
spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH); spd_byte0 &= 0xF; - if (spd_byte0 > 5){ + if (spd_byte0 > 5) { spd_byte0 = 5; } rate0 = REF_RATE[spd_byte0];
spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH); spd_byte1 &= 0xF; - if (spd_byte1 > 5){ + if (spd_byte1 > 5) { spd_byte1 = 5; } rate1 = REF_RATE[spd_byte1];
/* Use the faster rate (lowest number) */ - if (rate0 > rate1){ + if (rate0 > rate1) { rate0 = rate1; }
- msr = rdmsr(MC_CF07_DATA); - msr.lo|= ((rate0 * (GeodeLinkSpeed()/2))/16) << CF07_LOWER_REF_INT_SHIFT; - wrmsr(MC_CF07_DATA, msr); - } + msr = rdmsr(MC_CF07_DATA); + msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16) + << CF07_LOWER_REF_INT_SHIFT; + wrmsr(MC_CF07_DATA, msr); +}
+const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
-const uint8_t CASDDR[] = {5, 5, 2, 6, 3, 7, 4, 0}; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */ - -static void setCAS(void){ +static void setCAS(void) +{ /*;***************************************************************************** ;* ;* setCAS @@ -236,226 +238,220 @@
/************************** DIMM0 **********************************/ casmap0 = spd_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES); - if (casmap0 != 0xFF){ + if (casmap0 != 0xFF) { /* IF -.5 timing is supported, check -.5 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND); - if(spd_byte != 0){ + if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); - if (dimm_speed >= glspeed){ + dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + + (spd_byte & 0x0F))); + if (dimm_speed >= glspeed) { /* IF -1 timing is supported, check -1 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD); - if(spd_byte != 0){ + if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); - if (dimm_speed <= glspeed){ + dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + if (dimm_speed <= glspeed) { /* set we can use -.5 timing but not -1 */ - spd_byte = 31 - __builtin_clz((uint32_t)casmap0); /* just want bits in the lower byte since we have to cast to a 32 */ + spd_byte = 31 - __builtin_clz((uint32_t) casmap0); + /* just want bits in the lower byte since we have to cast to a 32 */ casmap0 &= 0xFF << (--spd_byte); } - } /*MIN_CYCLE_10 !=0 */ - } - else{ /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ - spd_byte = 31 - __builtin_clz((uint32_t)casmap0); /* just want bits in the lower byte since we have to cast to a 32 */ + } /*MIN_CYCLE_10 !=0 */ + } else { + /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ + spd_byte = 31 - __builtin_clz((uint32_t) casmap0); + /* just want bits in the lower byte since we have to cast to a 32 */ casmap0 &= 0xFF << (spd_byte); } - } /*MIN_CYCLE_05 !=0 */ + } /*MIN_CYCLE_05 !=0 */ + } else { /* No DIMM */ + casmap0 = 0; } - else{ /* No DIMM */ - casmap0=0; - }
/************************** DIMM1 **********************************/ casmap1 = spd_read_byte(DIMM1, SPD_ACCEPTABLE_CAS_LATENCIES); - if (casmap1 != 0xFF){ + if (casmap1 != 0xFF) { /* IF -.5 timing is supported, check -.5 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND); - if(spd_byte != 0){ + if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); - if (dimm_speed >= glspeed){ + dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + if (dimm_speed >= glspeed) { /* IF -1 timing is supported, check -1 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD); - if(spd_byte != 0){ + if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); - if (dimm_speed <= glspeed){ + dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + if (dimm_speed <= glspeed) { /* set we can use -.5 timing but not -1 */ - spd_byte =31 - __builtin_clz((uint32_t)casmap1); /* just want bits in the lower byte since we have to cast to a 32 */ + spd_byte = 31 - __builtin_clz((uint32_t) casmap1); + /* just want bits in the lower byte since we have to cast to a 32 */ casmap1 &= 0xFF << (--spd_byte); } - } /*MIN_CYCLE_10 !=0 */ - } - else{ /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ - spd_byte = 31 - __builtin_clz((uint32_t)casmap1); /* just want bits in the lower byte since we have to cast to a 32 */ + } /*MIN_CYCLE_10 !=0 */ + } else { + /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ + spd_byte = 31 - __builtin_clz((uint32_t) casmap1); + /* just want bits in the lower byte since we have to cast to a 32 */ casmap1 &= 0xFF << (spd_byte); } - } /*MIN_CYCLE_05 !=0 */ + } /*MIN_CYCLE_05 !=0 */ + } else { /* No DIMM */ + casmap1 = 0; } - else{ /* No DIMM */ - casmap1=0; - }
/********************* CAS_LAT MAP COMPARE ***************************/ - if (casmap0 == 0){ - spd_byte = CASDDR[__builtin_ctz((uint32_t)casmap1)]; - } - else if (casmap1 == 0){ - spd_byte = CASDDR[__builtin_ctz((uint32_t)casmap0)]; - } - else if ((casmap0 &= casmap1)){ - spd_byte = CASDDR[__builtin_ctz((uint32_t)casmap0)]; - } - else{ + if (casmap0 == 0) { + spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap1)]; + } else if (casmap1 == 0) { + spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)]; + } else if ((casmap0 &= casmap1)) { + spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)]; + } else { print_debug("DIMM CAS Latencies not compatible\r\n"); POST_CODE(ERROR_DIFF_DIMMS); __asm__ __volatile__("hlt\n"); }
- msr = rdmsr(MC_CF8F_DATA); msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT); msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT; wrmsr(MC_CF8F_DATA, msr); }
- -static void set_latencies(void){ +static void set_latencies(void) +{ uint32_t memspeed, dimm_setting; uint8_t spd_byte0, spd_byte1; msr_t msr;
- memspeed = GeodeLinkSpeed()/2; - dimm_setting=0; + memspeed = GeodeLinkSpeed() / 2; + dimm_setting = 0;
/* MC_CF8F setup */ /* tRAS */ spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; } - if (spd_byte0 < spd_byte1){ + if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; }
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ - spd_byte1 = (spd_byte0 * memspeed)/1000; - if(((spd_byte0 * memspeed)%1000)){ + spd_byte1 = (spd_byte0 * memspeed) / 1000; + if (((spd_byte0 * memspeed) % 1000)) { ++spd_byte1; } dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
- /* tRP */ spd_byte0 = spd_read_byte(DIMM0, SPD_tRP); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_tRP); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; } - if (spd_byte0 < spd_byte1){ + if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; }
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ - spd_byte1 = ((spd_byte0 >> 2) * memspeed)/1000; - if((((spd_byte0 >> 2) * memspeed)%1000)){ + spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000; + if ((((spd_byte0 >> 2) * memspeed) % 1000)) { ++spd_byte1; } dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
- /* tRCD */ spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; } - if (spd_byte0 < spd_byte1){ + if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; }
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ - spd_byte1 = ((spd_byte0 >> 2) * memspeed)/1000; - if((((spd_byte0 >> 2) * memspeed)%1000)){ + spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000; + if ((((spd_byte0 >> 2) * memspeed) % 1000)) { ++spd_byte1; } dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
- /* tRRD */ spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; } - if (spd_byte0 < spd_byte1){ + if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; }
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ - spd_byte1 = ((spd_byte0 >> 2) * memspeed)/1000; - if((((spd_byte0 >> 2) * memspeed)%1000)){ + spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000; + if ((((spd_byte0 >> 2) * memspeed) % 1000)) { ++spd_byte1; } dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
- /* tRC = tRP + tRAS */ - dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) + ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07)) \ - << CF8F_LOWER_ACT2ACTREF_SHIFT; + dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) + + ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07)) + << CF8F_LOWER_ACT2ACTREF_SHIFT;
- msr = rdmsr(MC_CF8F_DATA); msr.lo &= 0xF00000FF; msr.lo |= dimm_setting; - msr.hi |= CF8F_UPPER_REORDER_DIS_SET; + msr.hi |= CF8F_UPPER_REORDER_DIS_SET; wrmsr(MC_CF8F_DATA, msr);
/* MC_CF1017 setup */ /* tRFC */ spd_byte0 = spd_read_byte(DIMM0, SPD_tRFC); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_tRFC); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; } - if (spd_byte0 < spd_byte1){ + if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; }
- if (spd_byte0){ + if (spd_byte0) { /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ - spd_byte1 = (spd_byte0 * memspeed)/1000; - if(((spd_byte0 * memspeed)%1000)){ + spd_byte1 = (spd_byte0 * memspeed) / 1000; + if (((spd_byte0 * memspeed) % 1000)) { ++spd_byte1; } - } - else{ /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */ + } else { /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */ spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1; } - dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */ + dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */ msr = rdmsr(MC_CF1017_DATA); msr.lo &= ~(0x1F << CF1017_LOWER_REF2ACT_SHIFT); msr.lo |= dimm_setting; wrmsr(MC_CF1017_DATA, msr);
/* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200Mhz mem) other wise it stay default(1) */ - if (memspeed > 198){ + if (memspeed > 198) { msr = rdmsr(MC_CF1017_DATA); msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT); msr.lo |= 2 << CF1017_LOWER_WR_TO_RD_SHIFT; @@ -463,41 +459,45 @@ } }
-static void set_extended_mode_registers(void){ +static void set_extended_mode_registers(void) +{ uint8_t spd_byte0, spd_byte1; msr_t msr; spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; } spd_byte1 &= spd_byte0;
msr = rdmsr(MC_CF07_DATA); - if (spd_byte1 & 1){ /* Drive Strength Control */ + if (spd_byte1 & 1) { /* Drive Strength Control */ msr.lo |= CF07_LOWER_EMR_DRV_SET; } - if (spd_byte1 & 2){ /* FET Control */ + if (spd_byte1 & 2) { /* FET Control */ msr.lo |= CF07_LOWER_EMR_QFC_SET; } wrmsr(MC_CF07_DATA, msr); }
-static void EnableMTest (void){ +static void EnableMTest(void) +{ msr_t msr;
msr = rdmsr(GLCP_DELAY_CONTROLS); - msr.hi &= ~(7 << 20); /* clear bits 54:52 */ - if (GeodeLinkSpeed() < 200){ + msr.hi &= ~(7 << 20); /* clear bits 54:52 */ + if (GeodeLinkSpeed() < 200) { msr.hi |= 2 << 20; } wrmsr(GLCP_DELAY_CONTROLS, msr);
msr = rdmsr(MC_CFCLK_DBUG); - msr.hi |= CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET | CFCLK_UPPER_MTST_RBEX_EN_SET; + msr.hi |= + CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET | + CFCLK_UPPER_MTST_RBEX_EN_SET; msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET; wrmsr(MC_CFCLK_DBUG, msr);
@@ -513,10 +513,9 @@ msrnum = MC_CF1017_DATA; msr = rdmsr(msrnum); msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT); - if (GeodeLinkSpeed() < 334){ + if (GeodeLinkSpeed() < 334) { msr.lo |= (3 << CF1017_LOWER_RD_TMG_CTL_SHIFT); - } - else{ + } else { msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT); } wrmsr(msrnum, msr); @@ -525,50 +524,49 @@ msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); msr.lo &= ~0xF0; - msr.lo |= 0x40; /* set refresh to 4SDRAM clocks */ + msr.lo |= 0x40; /* set refresh to 4SDRAM clocks */ wrmsr(msrnum, msr);
/* Memory Interleave: Set HOI here otherwise default is LOI */ /* msrnum = MC_CF8F_DATA; - msr = rdmsr(msrnum); - msr.hi |= CF8F_UPPER_HOI_LOI_SET; - wrmsr(msrnum, msr); */ + msr = rdmsr(msrnum); + msr.hi |= CF8F_UPPER_HOI_LOI_SET; + wrmsr(msrnum, msr); */ }
- static void sdram_set_spd_registers(const struct mem_controller *ctrl) { uint8_t spd_byte;
- POST_CODE(POST_MEM_SETUP); // post_70h + POST_CODE(POST_MEM_SETUP); // post_70h
spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES); /* Check DIMM is not Register and not Buffered DIMMs. */ - if ((spd_byte != 0xFF) && (spd_byte & 3) ){ + if ((spd_byte != 0xFF) && (spd_byte & 3)) { print_debug("DIMM0 NOT COMPATIBLE\r\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); __asm__ __volatile__("hlt\n"); } spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES); - if ((spd_byte != 0xFF) && (spd_byte & 3)){ + if ((spd_byte != 0xFF) && (spd_byte & 3)) { print_debug("DIMM1 NOT COMPATIBLE\r\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); __asm__ __volatile__("hlt\n"); }
- POST_CODE(POST_MEM_SETUP2); // post_72h + POST_CODE(POST_MEM_SETUP2); // post_72h
/* Check that the memory is not overclocked. */ checkDDRMax();
/* Size the DIMMS */ - POST_CODE(POST_MEM_SETUP3); // post_73h + POST_CODE(POST_MEM_SETUP3); // post_73h auto_size_dimm(DIMM0); - POST_CODE(POST_MEM_SETUP4); // post_74h + POST_CODE(POST_MEM_SETUP4); // post_74h auto_size_dimm(DIMM1);
/* Set CAS latency */ - POST_CODE(POST_MEM_SETUP5); // post_75h + POST_CODE(POST_MEM_SETUP5); // post_75h setCAS();
/* Set all the other latencies here (tRAS, tRP....) */ @@ -601,73 +599,66 @@ ;* 9) MRS w/ memory config & reset DLL clear ;* 8) DDR SDRAM ready for normal operation ;********************************************************************/ - POST_CODE(POST_MEM_ENABLE); // post_76h + POST_CODE(POST_MEM_ENABLE); // post_76h
/* Only enable MTest for TLA memory debug */ - /*EnableMTest();*/ + /*EnableMTest(); */
/* If both Page Size = "Not Installed" we have a problems and should halt. */ msr = rdmsr(MC_CF07_DATA); - if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) \ - == ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))){ + if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == + ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) { print_debug("No memory in the system\r\n"); POST_CODE(ERROR_NO_DIMMS); __asm__ __volatile__("hlt\n"); }
- /* Set CKEs */ + /* Set CKEs */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1); wrmsr(msrnum, msr);
- /* Force Precharge All on next command, EMRS */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo |= CFCLK_LOWER_FORCE_PRE_SET; - wrmsr(msrnum,msr); + wrmsr(msrnum, msr);
- /* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */ - msrnum = MC_CF07_DATA; + msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET; wrmsr(msrnum, msr); msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET); wrmsr(msrnum, msr);
- /* Clear Force Precharge All */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET; wrmsr(msrnum, msr);
- /* MRS Reset DLL - set */ msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET; - wrmsr(msrnum,msr); + wrmsr(msrnum, msr); msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET); wrmsr(msrnum, msr);
- /* 2us delay (200 clocks @ 200Mhz). We probably really don't need this but.... better safe. */ /* Wait 2 PORT61 ticks. between 15us and 30us */ /* This would be endless if the timer is stuck. */ - while ((inb(0x61))); /* find the first edge */ - while (!(~inb(0x61))); + while ((inb(0x61))) ; /* find the first edge */ + while (!(~inb(0x61))) ;
- /* Force Precharge All on the next command, auto-refresh */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo |= CFCLK_LOWER_FORCE_PRE_SET; wrmsr(msrnum, msr);
- /* Manually AUTO refresh #1 */ /* If auto refresh was not enabled above we would need to do 8 refreshes to prime the pump before these 2. */ msrnum = MC_CF07_DATA; @@ -683,7 +674,6 @@ msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET; wrmsr(msrnum, msr);
- /* Manually AUTO refresh */ /* The MC should insert the right delay between the refreshes */ msrnum = MC_CF07_DATA; @@ -693,7 +683,6 @@ msr.lo &= ~CF07_LOWER_REF_TEST_SET; wrmsr(msrnum, msr);
- /* MRS Reset DLL - clear */ msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); @@ -702,17 +691,16 @@ msr.lo &= ~CF07_LOWER_PROG_DRAM_SET; wrmsr(msrnum, msr);
- /* Allow MC to tristate during idle cycles with MTEST OFF */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET; wrmsr(msrnum, msr);
- /* Disable SDCLK DIMM1 slot if no DIMM installed to save power. */ msr = rdmsr(MC_CF07_DATA); - if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) == (7 << CF07_UPPER_D1_PSZ_SHIFT)){ + if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) == + (7 << CF07_UPPER_D1_PSZ_SHIFT)) { msrnum = GLCP_DELAY_CONTROLS; msr = rdmsr(msrnum); msr.hi |= (1 << 23); /* SDCLK bit for 2.0 */ @@ -720,11 +708,10 @@ }
/* Set PMode0 Sensitivity Counter */ - msr.lo = 0; /* pmode 0=0 most aggressive */ + msr.lo = 0; /* pmode 0=0 most aggressive */ msr.hi = 0x200; /* pmode 1=200h */ wrmsr(MC_CF_PMCTR, msr);
- /* Set PMode1 Up delay enable */ msrnum = MC_CF1017_DATA; msr = rdmsr(msrnum); @@ -732,15 +719,15 @@ wrmsr(msrnum, msr);
print_debug("DRAM controller init done.\r\n"); - POST_CODE(POST_MEM_SETUP_GOOD); //0x7E + POST_CODE(POST_MEM_SETUP_GOOD); //0x7E
/* make sure there is nothing stale in the cache */ - /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n");*/ + /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
/* The RAM dll needs a write to lock on so generate a few dummy writes */ /* Note: The descriptor needs to be enabled to point at memory */ volatile unsigned long *ptr; - for (i=0;i<5;i++) { + for (i = 0; i < 5; i++) { ptr = (void *)i; *ptr = (unsigned long)i; } @@ -751,19 +738,18 @@ if ((msr.lo & 0x7FF) == 0x104) {
/* If you had it you would need to clear out the fail boot count flag */ - /* (depending on where it counts from etc).*/ + /* (depending on where it counts from etc). */
/* The reset we are about to perform clears the PM_SSC register in the */ - /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */ - /* it would do a normal boot */ + /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */ + /* it would do a normal boot */
/* Reset the system */ msrnum = MDD_SOFT_RESET; msr = rdmsr(msrnum); msr.lo |= 1; wrmsr(msrnum, msr); -} + } print_debug("RAM DLL lock\r\n");
- }
Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.h =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.h 2007-05-10 18:00:24 UTC (rev 2648) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.h 2007-05-10 18:16:03 UTC (rev 2649) @@ -27,4 +27,4 @@ uint16_t channel0[DIMM_SOCKETS]; };
-#endif /* RAMINIT_H */ +#endif /* RAMINIT_H */