[coreboot] Patch merged into coreboot/master: ca6e1f6 AMD S3: Program the flash in a bigger data packet

the following patch was just integrated into master:
commit ca6e1f6c04c96c435bdbf30a1b88cab0e5be330b
Author: Zheng Bao 
Date:   Sun Feb 17 17:27:46 2013 +0800

AMD S3: Program the flash in a bigger data packet

According to spi.c in src/southbridge/amd/agesa/hudson
    readwrite = (bytesin + readoffby1) << 4 | bytesout;
    We can see that Hudson limits the SPI programming data
    packet size as 15.

We used to write data to SPI in dword mode. It didn't
    take full advantage of the data packet size. We need to
    leverage that to speed up programming time.

Change-Id: I615e3c8e754e58702247bc26cfffbedaf5827ea8
    Signed-off-by: Zheng Bao 
    Signed-off-by: Zheng Bao 
    Reviewed-on: http://review.coreboot.org/2306
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin 
    Reviewed-by: Martin Roth

See http://review.coreboot.org/2306 for details.

-gerrit