We will try to debug this after the Chinese New Year.
Now I am debugging the shiner (RS780/SB700). The board will be returned in a week, so I have to focus on this. Now most of the feature is working, except VGA.
Zheng
-----Original Message----- From: Marc Jones [mailto:marcj303@gmail.com] Sent: Wednesday, January 21, 2009 9:58 AM To: Carl-Daniel Hailfinger Cc: Rudolf Marek; Bao, Zheng; Coreboot Subject: Re: [coreboot] 4 GB RAM failure on DBM690T target (690G/SB600)
On Tue, Jan 20, 2009 at 6:50 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 20.01.2009 17:13, Rudolf Marek wrote:
I'm not totally sure the ACPI code is hard coded to 1 GB. The
default
values in the ACPI code code correspond to 1 GB and there is some
code
which will calculate BIOS memory location from TOM and TOM2. I could
not
find any place where TOM and TOM2 are updated,
its in acpi-k8.c in amd directory. Its in ssdt table.
Thanks. Unfortunately, the situation is more complicated on DBM690T. TOM (the top below 4 GB) is stored twice, once in the SSDT (modified automatically) and once in the DSDT (unmodified). TOM2 is only stored
in
the DSDT (unmodified). The (correct) value of TOM in the SSDT is
ignored
and the (incorrect) values of TOM/TOM2 in the DSDT are used.
This sounds like a oversite. Maybe the AMD BTDC guys can help. Marc