Marc Jones wrote:
]> 1) Work around coreboot resource allocation problem that causes ]> overlap of PCIe MMIO space and graphics MMIO space. ] ]Why isn't this covered by the bus resource allocation for MMCONF? I ]think that this should handle the situation. How does the overlap ]happen?
Hello Marc,
I think the short answer is the mmconf range is added to a device that is skipped by the bus resource allocation code. The mmconf range is added to APIC_CLUSTER:0, which is not looked at by the resource allocation code. Here is what I found a while back:
Why does the current code for handling fixed resources allow the mmconf space to get allocated to a PCI device? Function avoid_fixed_resources calls function constrain_resources, which recursively searches the device tree for fixed io and memory resources. The ioapic fixed memory address is found and avoided during the recursive search because this southbridge device is below the level where the search starts. On the other hand, the mmconf fixed resource is added from the northbridge code, and falls under 'APIC_CLUSTER: 0'. This device is not part of the search for two reasons. One is that it is not at or below 'pci_domain 0' in the device tree. Another reason is that its type is APIC_CLUSTER and not PCI_DOMAIN.
The last patch I sent includes a better workaround. To avoid modification of the resource allocation code, mmconf is moved from e0000000 to f8000000. This is the solution I attempted originally, but had to set aside until a couple of mmio problems were fixed.
Thanks, Scott