Re: [coreboot] patch: dbe62 boots to FILO!

[Carl-Daniel Hailfinger]

Great!

On 03.04.2008 08:04, ron minnich wrote:
> now how do we get a disk to boot? All we have is USB :-)
> With this set of changes dbe62 gets to a FILO prompt.
>
> Set manual settings for dbe62 PLL; the auto settings are giving 
> slightly wrong values
>
> Add call to dumplxmsr in dbe62 initram main()
>
> Add dumplxmsrs function to geodelx raminit support code
>
> Correct spelling of CAS.
>
> The big one: set spd variables correctly.
>
> The not so big one: there is a bug in com2 enable I don't understand.
> For now comment out two offending lines. The cs5536 debug prints
> should be reduced later.
>
> Signed-off-by: Ronald G. Minnich

The patch looks nice, but there are a few small problems.
> Index: southbridge/amd/cs5536/cs5536.c
>
> --- southbridge/amd/cs5536/cs5536.c	(revision 637)
> +++ southbridge/amd/cs5536/cs5536.c	(working copy)
> @@ -258,6 +258,7 @@
>
> /* COM1 */
>    if (sb->com1_enable) {
> printk(BIOS_SPEW, "uarts_init: enable com1\n");
> /* Set the address. */
> switch (sb->com1_address) {
> case 0x3F8:
>
> @@ -308,6 +309,7 @@
>    	wrmsr(MDD_UART1_CONF, msr);
>    } else {
>    	/* Reset and disable COM1. */
> printk(BIOS_SPEW, "uarts_init: disable com1\n");
> msr = rdmsr(MDD_UART1_CONF);
> msr.lo = 1;			/* Reset */
> wrmsr(MDD_UART1_CONF, msr);
>
> @@ -322,6 +324,7 @@
>
> /* COM2 */
>    if (sb->com2_enable) {
> printk(BIOS_SPEW, "uarts_init: enable com2\n");
> switch (sb->com2_address) {
> case 0x3F8:
> 	addr = 7;
>
> @@ -339,28 +342,31 @@
>    	msr = rdmsr(MDD_LEG_IO);
>    	msr.lo |= addr << 20;
>    	wrmsr(MDD_LEG_IO, msr);
> printk(BIOS_SPEW, "uarts_init: wrote com2 address 0x%x\n", sb->com2_address);
>
> /* Set the IRQ. */
> msr = rdmsr(MDD_IRQM_YHIGH);
> msr.lo |= sb->com2_irq << 28;
> wrmsr(MDD_IRQM_YHIGH, msr);

Empty line removed. Intentional?
> printk(BIOS_SPEW, "uarts_init: set com2 irq\n");
> /* GPIO3 - UART2_RX */
> /* Set: Output Enable (0x4) */
> outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
> printk(BIOS_SPEW, "uarts_init: set output enable\n");
> /* Set: OUTAUX1 Select (0x10) */
> outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);

Same here.
> printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n");
> /* GPIO4 - UART2_TX */
> /* Set: Input Enable (0x20) */
> outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
> printk(BIOS_SPEW, "uarts_init: set com2 input enable\n");
> /* Set: INAUX1 Select (0x34) */
> outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);

Same here.
> +//		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX2_SELECT);
> +//		printk(BIOS_SPEW, "uarts_init: set INAUX2 for com2\n");
>    	/* Set: GPIO 3 + 3 Pull Up (0x18) */
>    	outl(GPIOL_3_SET | GPIOL_4_SET,
>    	     gpio_addr + GPIOL_PULLUP_ENABLE);

Same here.
> printk(BIOS_SPEW, "uarts_init: set pullup com2\n");
> /* Enable COM2.
> Bit 1 = device enable
>
> @@ -369,7 +375,9 @@
>    	msr.lo = (1 << 4) | (1 << 1);
>    	msr.hi = 0;
>    	wrmsr(MDD_UART2_CONF, msr);
> printk(BIOS_SPEW, "uarts_init: com2 enabled\n");
> } else {
> printk(BIOS_SPEW, "uarts_init: disable com2\n");
> /* Reset and disable COM2. */
> msr = rdmsr(MDD_UART2_CONF);
> msr.lo = 1;			/* Reset */
>
> @@ -619,12 +627,15 @@
>    setup_i8259();
>    lpc_init(sb);
>    uarts_init(sb);

Same here.
> printk(BIOS_SPEW, "cs5536: done uarts_init\n");
> if (sb->enable_gpio_int_route) {
> printk(BIOS_SPEW, "cs5536: call vr_write\n");
>
> vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
> 	 (sb->enable_gpio_int_route & 0xFFFF));
> printk(BIOS_SPEW, "cs5536: done first call vr_write\n");
>
> vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
> 	 (sb->enable_gpio_int_route >> 16));
> printk(BIOS_SPEW, "cs5536: done second call vr_write\n");
>
> }
>
> printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n",
> Index: mainboard/artecgroup/dbe62/initram.c
>
> --- mainboard/artecgroup/dbe62/initram.c	(revision 637)
> +++ mainboard/artecgroup/dbe62/initram.c	(working copy)
> @@ -33,9 +33,9 @@
>  #include <northbridge/amd/geodelx/raminit.h>
>  #include <spd.h>
>
> -#define MANUALCONF 0		/* Do automatic strapped PLL config */
> -#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
> -#define PLLMSRLO 0x02000030
> +#define MANUALCONF 1		/* Do automatic strapped PLL config */

Change the comment to "...manual strapped..."
> +#define PLLMSRHI 0x000003d9	/* manual settings for the PLL */
> +#define PLLMSRLO 0x07de0080	/* from factory bios */

Hey, where did the fuctory go?
> #define DIMM0 ((u8) 0xA0)
>  #define DIMM1 ((u8) 0xA2)
>
> @@ -50,20 +50,68 @@
>    u8 address;
>    u8 data;
>  };
> +/*
> +ok, This is what I came up with. I would be interested in the results.

Please explain that comment.
> +spd : value(hex)
> +4: 8
> +5: 1
> +9: <= 7
> +12: 82
> +17: 4
> +31: 40
> +18: 10
> +23: 0
> +25: 0
> +27: 58
> +28: 3c
> +29: 58
> +30: 2d
> +42:4b
>
> +I may have missed one so let me know. Also you might find this document helpful.
> +*/
>
> /* Save space by using a short list of SPD values used by Geode LX Memory init */
>  static const struct spd_entry spd_table[] = {
> +#if 1
> /* these were missing too :-) */
> {SPD_MEMORY_TYPE, 7},
> {SPD_NUM_ROWS, 13},
> /* from marc */
> {42, 0x4b},

42 is SPD_tRFC.
> {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
> {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x40},
> {SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, 0x2d},

This is SPD_tRAS.
> {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/
> {SPD_MIN_RAS_TO_CAS_DELAY, 0x58},
> {SPD_MIN_ROWACTIVE_TO_ROWACTIVE, 0x3c},

This is SPD_tRRD.
> {SPD_MIN_ROW_PRECHARGE_TIME, 0x58},

This is SPD_tRP.
> {SPD_NUM_BANKS_PER_SDRAM, 0x4},
> {SPD_NUM_COLUMNS, 0x8},
> {SPD_NUM_DIMM_BANKS, 0x1},
> {SPD_REFRESH, 0x82},
> {SPD_SDRAM_CYCLE_TIME_2ND, 0x0},
> {SPD_SDRAM_CYCLE_TIME_3RD, 0x0},
> /* these were missing and kind of important */
> {SPD_tRAS, 40},

Here SPD_tRAS is set again, but never used.
> {SPD_tRCD, 15},
> {SPD_tRFC, 70},

Here SPD_tRFC is set again, but this second value is never used.
> {SPD_tRP, 15},

Same for SPD_tRP.
> {SPD_tRRD, 10},

Same for SPD_tRRD.
> +#endif
> +#if 0
>    {SPD_ACCEPTABLE_CAS_LATENCIES, 0xe},
>    {SPD_BANK_DENSITY, 0x40},
>    {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff},
>    {SPD_MEMORY_TYPE, 7},
> {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */
> {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */
> {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10},
> {SPD_MODULE_ATTRIBUTES, 0xff},
> {SPD_NUM_BANKS_PER_SDRAM, 4},
> {SPD_PRIMARY_SDRAM_WIDTH, 8},
> {SPD_NUM_COLUMNS, 0xa},
> {SPD_NUM_DIMM_BANKS, 1},
> {SPD_NUM_COLUMNS, 0xa},
> {SPD_NUM_ROWS, 13},
> {SPD_PRIMARY_SDRAM_WIDTH, 8},
> {SPD_REFRESH, 0x3a},
> {SPD_SDRAM_CYCLE_TIME_2ND, 60},
> {SPD_SDRAM_CYCLE_TIME_3RD, 75},
>
> @@ -72,6 +120,7 @@
>    {SPD_tRFC, 70},
>    {SPD_tRP, 15},
>    {SPD_tRRD, 10},
> +#endif

Can't we just merge the SPD array variants above? Introducing #if 0 is
not really something we can explain later.
> };
>
> /**
> @@ -124,6 +173,8 @@
>    */
>  int main(void)
>  {
> void dumplxmsrs(int level);

Please remove the level argument.
> u8 smb_devices[] =  {
>   DIMM0, DIMM1
>  };
>
> @@ -151,8 +202,11 @@
>    sdram_enable(DIMM0, DIMM1);
>    printk(BIOS_DEBUG, "done sdram enable\n");
> dumplxmsrs(BIOS_DEBUG);
> /* Check low memory */
> ram_check(0x00000000, 640*1024);
>
> /* passed. Don't bother any more */
>
> /* Note that the range 0x87000 will fail; that's the stack! */
>
> /*	ram_check(0x00000000, 640*1024);*/
>
> printk(BIOS_DEBUG, "stage1 returns\n");
> return 0;
> Index: northbridge/amd/geodelx/raminit.c
>
> --- northbridge/amd/geodelx/raminit.c	(revision 637)
> +++ northbridge/amd/geodelx/raminit.c	(working copy)
> @@ -35,6 +35,42 @@
>
> u8 spd_read_byte(u16 device, u8 address);
>
> +/**
> Dump key MSR values for ram init. You can call this function and then use it to
> compare to a fuctory bios setting.
> @param level printk level
> */
>
> +void dumplxmsrs(int level)

level should be hardcoded.
> +{
> static unsigned long msrs[] = {
>    	MC_CF07_DATA, 
>    	MC_CF8F_DATA, 
>    	MC_CF1017_DATA, 
>    	GLCP_DELAY_CONTROLS, 
>    	MC_CFCLK_DBUG, 
>    	MC_CF_PMCTR,
> GLCP_SYS_RSTPLL
> };
> static char *msrnames[] = {
>    	"MC_CF07_DATA", 
>    	"MC_CF8F_DATA", 
>    	"MC_CF1017_DATA", 
>    	"GLCP_DELAY_CONTROLS", 
>    	"MC_CFCLK_DBUG", 
>    	"MC_CF_PMCTR",
> "PLL reg"
> };
> int i;
> for(i = 0; i < sizeof(msrs)/sizeof(msrs[0]); i++){

Use ARRAY_SIZE instead.
> struct msr msr;
> msr = rdmsr(msrs[i]);
> printk(level, "(%lx): %x.%x\n",  msrs[i], msr.hi, msr.lo);
> }
>
> +}
>  /**
> Halt and Catch Fire. Print an error, then loop, sending NULLs on serial port,
> to ensure the message is visible.
>
> @@ -389,7 +425,7 @@
>    	hlt();
>    }
> printk(BIOS_DEBUG, "Set cas latency to %x\n", spd_byte);
> printk(BIOS_DEBUG, "Set CAS latency to %x\n", spd_byte);
> msr = rdmsr(MC_CF8F_DATA);
> msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
> msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;

Otherwise, the patch looks fine.

Reworked patch follows. It should be identical from a code point of
view, but it would be great if you could test anyway.
Please note that the patch is against HEAD. Same patch is also attached.

Signed-off-by: Carl-Daniel Hailfinger

Index: LinuxBIOSv3-dbe62/southbridge/amd/cs5536/cs5536.c
===================================================================
--- LinuxBIOSv3-dbe62/southbridge/amd/cs5536/cs5536.c	(Revision 647)
+++ LinuxBIOSv3-dbe62/southbridge/amd/cs5536/cs5536.c	(Arbeitskopie)
@@ -258,6 +258,7 @@

/* COM1 */
    if (sb->com1_enable) {
+		printk(BIOS_SPEW, "uarts_init: enable com1\n");
    	/* Set the address. */
    	switch (sb->com1_address) {
    	case 0x3F8:
@@ -308,6 +309,7 @@
    	wrmsr(MDD_UART1_CONF, msr);
    } else {
    	/* Reset and disable COM1. */
+		printk(BIOS_SPEW, "uarts_init: disable com1\n");
    	msr = rdmsr(MDD_UART1_CONF);
    	msr.lo = 1;			/* Reset */
    	wrmsr(MDD_UART1_CONF, msr);
@@ -322,6 +324,7 @@

/* COM2 */
    if (sb->com2_enable) {
+		printk(BIOS_SPEW, "uarts_init: enable com2\n");
    	switch (sb->com2_address) {
    	case 0x3F8:
    		addr = 7;
@@ -339,27 +342,33 @@
    	msr = rdmsr(MDD_LEG_IO);
    	msr.lo |= addr << 20;
    	wrmsr(MDD_LEG_IO, msr);
+		printk(BIOS_SPEW, "uarts_init: wrote com2 address 0x%x\n", sb->com2_address);

/* Set the IRQ. */
    	msr = rdmsr(MDD_IRQM_YHIGH);
    	msr.lo |= sb->com2_irq << 28;
    	wrmsr(MDD_IRQM_YHIGH, msr);
+		printk(BIOS_SPEW, "uarts_init: set com2 irq\n");

/* GPIO3 - UART2_RX */
    	/* Set: Output Enable (0x4) */
    	outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
+		printk(BIOS_SPEW, "uarts_init: set output enable\n");
    	/* Set: OUTAUX1 Select (0x10) */
    	outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
+		printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n");

/* GPIO4 - UART2_TX */
    	/* Set: Input Enable (0x20) */
    	outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
+		printk(BIOS_SPEW, "uarts_init: set com2 input enable\n");
    	/* Set: INAUX1 Select (0x34) */
-		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
-
+//		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX2_SELECT);
+//		printk(BIOS_SPEW, "uarts_init: set INAUX2 for com2\n");
    	/* Set: GPIO 3 + 3 Pull Up (0x18) */
    	outl(GPIOL_3_SET | GPIOL_4_SET,
    	     gpio_addr + GPIOL_PULLUP_ENABLE);
+		printk(BIOS_SPEW, "uarts_init: set pullup com2\n");

/* Enable COM2.
    	 *
@@ -369,7 +378,9 @@
    	msr.lo = (1 << 4) | (1 << 1);
    	msr.hi = 0;
    	wrmsr(MDD_UART2_CONF, msr);
+		printk(BIOS_SPEW, "uarts_init: com2 enabled\n");
    } else {
+		printk(BIOS_SPEW, "uarts_init: disable com2\n");
    	/* Reset and disable COM2. */
    	msr = rdmsr(MDD_UART2_CONF);
    	msr.lo = 1;			/* Reset */
@@ -620,11 +631,15 @@
    lpc_init(sb);
    uarts_init(sb);

+	printk(BIOS_SPEW, "cs5536: done uarts_init\n");
    if (sb->enable_gpio_int_route) {
+		printk(BIOS_SPEW, "cs5536: call vr_write\n");
    	vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
    		 (sb->enable_gpio_int_route & 0xFFFF));
+		printk(BIOS_SPEW, "cs5536: done first call vr_write\n");
    	vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
    		 (sb->enable_gpio_int_route >> 16));
+		printk(BIOS_SPEW, "cs5536: done second call vr_write\n");
    }

printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n",
Index: LinuxBIOSv3-dbe62/mainboard/artecgroup/dbe62/initram.c
===================================================================
--- LinuxBIOSv3-dbe62/mainboard/artecgroup/dbe62/initram.c	(Revision 647)
+++ LinuxBIOSv3-dbe62/mainboard/artecgroup/dbe62/initram.c	(Arbeitskopie)
@@ -33,9 +33,9 @@
 #include <northbridge/amd/geodelx/raminit.h>
 #include <spd.h>

-#define MANUALCONF 0		/* Do automatic strapped PLL config */
-#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
-#define PLLMSRLO 0x02000030
+#define MANUALCONF 1		/* Do manual strapped PLL config */
+#define PLLMSRHI 0x000003d9	/* manual settings for the PLL */
+#define PLLMSRLO 0x07de0080	/* from fuctory bios */
 #define DIMM0 ((u8) 0xA0)
 #define DIMM1 ((u8) 0xA2)

@@ -50,28 +50,45 @@
    u8 address;
    u8 data;
 };
+/*
+ok, This is what I came up with. I would be interested in the results.
+spd : value(hex)
+4: 8
+5: 1
+9: <= 7
+12: 82
+17: 4
+31: 40
+18: 10
+23: 0
+25: 0
+27: 58
+28: 3c
+29: 58
+30: 2d
+42:4b

+I may have missed one so let me know. Also you might find this document helpful.
+*/
+
 /* Save space by using a short list of SPD values used by Geode LX Memory init */
 static const struct spd_entry spd_table[] = {
-	{SPD_ACCEPTABLE_CAS_LATENCIES, 0xe},
-	{SPD_BANK_DENSITY, 0x40},
-	{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff},
+	{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x40}, /* SPD_BANK_DENSITY */
+	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/
+	{SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
    {SPD_MEMORY_TYPE, 7},
-	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */
-	{SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */
    {SPD_NUM_BANKS_PER_SDRAM, 4},
-	{SPD_PRIMARY_SDRAM_WIDTH, 8},
    {SPD_NUM_DIMM_BANKS, 1},
-	{SPD_NUM_COLUMNS, 0xa},
+	{SPD_NUM_COLUMNS, 0x8},
    {SPD_NUM_ROWS, 13},
-	{SPD_REFRESH, 0x3a},
-	{SPD_SDRAM_CYCLE_TIME_2ND, 60},
-	{SPD_SDRAM_CYCLE_TIME_3RD, 75},
-	{SPD_tRAS, 40},
-	{SPD_tRCD, 15},
-	{SPD_tRFC, 70},
-	{SPD_tRP, 15},
-	{SPD_tRRD, 10},
+	{SPD_REFRESH, 0x82},
+	{SPD_SDRAM_CYCLE_TIME_2ND, 0x0},
+	{SPD_SDRAM_CYCLE_TIME_3RD, 0x0},
+	{SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, 0x2d}, /* SPD_tRAS */
+	{SPD_MIN_RAS_TO_CAS_DELAY, 0x58}, /* SPD_tRCD */
+	{SPD_tRFC, 0x4b},
+	{SPD_MIN_ROW_PRECHARGE_TIME, 0x58}, /* SPD_tRP */
+	{SPD_MIN_ROWACTIVE_TO_ROWACTIVE, 0x3c}, /* SPD_tRRD */
 };

/**
@@ -124,6 +141,8 @@
   */
 int main(void)
 {
+	void dumplxmsrs(void);
+
    u8 smb_devices[] =  {
    	DIMM0, DIMM1
    };
@@ -151,8 +170,11 @@
    sdram_enable(DIMM0, DIMM1);
    printk(BIOS_DEBUG, "done sdram enable\n");

+	dumplxmsrs();
    /* Check low memory */
-	ram_check(0x00000000, 640*1024);
+	/* passed. Don't bother any more */
+	/* Note that the range 0x87000 will fail; that's the stack! */
+	/*	ram_check(0x00000000, 640*1024);*/

printk(BIOS_DEBUG, "stage1 returns\n");
    return 0;
Index: LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c
===================================================================
--- LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c	(Revision 647)
+++ LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c	(Arbeitskopie)
@@ -35,6 +35,43 @@

u8 spd_read_byte(u16 device, u8 address);

+
+/** 
+ * Dump key MSR values for ram init. You can call this function and then use it to 
+ * compare to a fuctory bios setting.
+ * @param level printk level
+ */
+void dumplxmsrs(void)
+{
+	static unsigned long msrs[] = {
+        	MC_CF07_DATA, 
+        	MC_CF8F_DATA, 
+        	MC_CF1017_DATA, 
+        	GLCP_DELAY_CONTROLS, 
+        	MC_CFCLK_DBUG, 
+        	MC_CF_PMCTR,
+		GLCP_SYS_RSTPLL
+	};
+	static char *msrnames[] = {
+        	"MC_CF07_DATA", 
+        	"MC_CF8F_DATA", 
+        	"MC_CF1017_DATA", 
+        	"GLCP_DELAY_CONTROLS", 
+        	"MC_CFCLK_DBUG", 
+        	"MC_CF_PMCTR",
+		"PLL reg"
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(msrs); i++) {
+		struct msr msr;
+		msr = rdmsr(msrs[i]);
+		printk(BIOS_DEBUG, "%s (%lx): %x.%x\n",  msrnames[i], msrs[i],
+			msr.hi, msr.lo);
+	}
+
+}
+
 /**
  * Halt and Catch Fire. Print an error, then loop, sending NULLs on
  * serial port, to ensure the message is visible.
@@ -387,7 +424,7 @@
    	hlt();
    }

-	printk(BIOS_DEBUG, "Set cas latency to %x\n", spd_byte);
+	printk(BIOS_DEBUG, "Set CAS latency to %x\n", spd_byte);
    msr = rdmsr(MC_CF8F_DATA);
    msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
    msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;

Index: LinuxBIOSv3-dbe62/southbridge/amd/cs5536/cs5536.c
===================================================================
--- LinuxBIOSv3-dbe62/southbridge/amd/cs5536/cs5536.c	(Revision 647)
+++ LinuxBIOSv3-dbe62/southbridge/amd/cs5536/cs5536.c	(Arbeitskopie)
@@ -258,6 +258,7 @@

/* COM1 */
    if (sb->com1_enable) {
+		printk(BIOS_SPEW, "uarts_init: enable com1\n");
    	/* Set the address. */
    	switch (sb->com1_address) {
    	case 0x3F8:
@@ -308,6 +309,7 @@
    	wrmsr(MDD_UART1_CONF, msr);
    } else {
    	/* Reset and disable COM1. */
+		printk(BIOS_SPEW, "uarts_init: disable com1\n");
    	msr = rdmsr(MDD_UART1_CONF);
    	msr.lo = 1;			/* Reset */
    	wrmsr(MDD_UART1_CONF, msr);
@@ -322,6 +324,7 @@

/* COM2 */
    if (sb->com2_enable) {
+		printk(BIOS_SPEW, "uarts_init: enable com2\n");
    	switch (sb->com2_address) {
    	case 0x3F8:
    		addr = 7;
@@ -339,27 +342,33 @@
    	msr = rdmsr(MDD_LEG_IO);
    	msr.lo |= addr << 20;
    	wrmsr(MDD_LEG_IO, msr);
+		printk(BIOS_SPEW, "uarts_init: wrote com2 address 0x%x\n", sb->com2_address);

/* Set the IRQ. */
    	msr = rdmsr(MDD_IRQM_YHIGH);
    	msr.lo |= sb->com2_irq << 28;
    	wrmsr(MDD_IRQM_YHIGH, msr);
+		printk(BIOS_SPEW, "uarts_init: set com2 irq\n");

/* GPIO3 - UART2_RX */
    	/* Set: Output Enable (0x4) */
    	outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
+		printk(BIOS_SPEW, "uarts_init: set output enable\n");
    	/* Set: OUTAUX1 Select (0x10) */
    	outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
+		printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n");

/* GPIO4 - UART2_TX */
    	/* Set: Input Enable (0x20) */
    	outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
+		printk(BIOS_SPEW, "uarts_init: set com2 input enable\n");
    	/* Set: INAUX1 Select (0x34) */
-		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
-
+//		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX2_SELECT);
+//		printk(BIOS_SPEW, "uarts_init: set INAUX2 for com2\n");
    	/* Set: GPIO 3 + 3 Pull Up (0x18) */
    	outl(GPIOL_3_SET | GPIOL_4_SET,
    	     gpio_addr + GPIOL_PULLUP_ENABLE);
+		printk(BIOS_SPEW, "uarts_init: set pullup com2\n");

/* Enable COM2.
    	 *
@@ -369,7 +378,9 @@
    	msr.lo = (1 << 4) | (1 << 1);
    	msr.hi = 0;
    	wrmsr(MDD_UART2_CONF, msr);
+		printk(BIOS_SPEW, "uarts_init: com2 enabled\n");
    } else {
+		printk(BIOS_SPEW, "uarts_init: disable com2\n");
    	/* Reset and disable COM2. */
    	msr = rdmsr(MDD_UART2_CONF);
    	msr.lo = 1;			/* Reset */
@@ -620,11 +631,15 @@
    lpc_init(sb);
    uarts_init(sb);

+	printk(BIOS_SPEW, "cs5536: done uarts_init\n");
    if (sb->enable_gpio_int_route) {
+		printk(BIOS_SPEW, "cs5536: call vr_write\n");
    	vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
    		 (sb->enable_gpio_int_route & 0xFFFF));
+		printk(BIOS_SPEW, "cs5536: done first call vr_write\n");
    	vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
    		 (sb->enable_gpio_int_route >> 16));
+		printk(BIOS_SPEW, "cs5536: done second call vr_write\n");
    }

printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n",
Index: LinuxBIOSv3-dbe62/mainboard/artecgroup/dbe62/initram.c
===================================================================
--- LinuxBIOSv3-dbe62/mainboard/artecgroup/dbe62/initram.c	(Revision 647)
+++ LinuxBIOSv3-dbe62/mainboard/artecgroup/dbe62/initram.c	(Arbeitskopie)
@@ -33,9 +33,9 @@
 #include <northbridge/amd/geodelx/raminit.h>
 #include <spd.h>

-#define MANUALCONF 0		/* Do automatic strapped PLL config */
-#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
-#define PLLMSRLO 0x02000030
+#define MANUALCONF 1		/* Do manual strapped PLL config */
+#define PLLMSRHI 0x000003d9	/* manual settings for the PLL */
+#define PLLMSRLO 0x07de0080	/* from fuctory bios */
 #define DIMM0 ((u8) 0xA0)
 #define DIMM1 ((u8) 0xA2)

@@ -50,28 +50,45 @@
    u8 address;
    u8 data;
 };
+/*
+ok, This is what I came up with. I would be interested in the results.
+spd : value(hex)
+4: 8
+5: 1
+9: <= 7
+12: 82
+17: 4
+31: 40
+18: 10
+23: 0
+25: 0
+27: 58
+28: 3c
+29: 58
+30: 2d
+42:4b

+I may have missed one so let me know. Also you might find this document helpful.
+*/
+
 /* Save space by using a short list of SPD values used by Geode LX Memory init */
 static const struct spd_entry spd_table[] = {
-	{SPD_ACCEPTABLE_CAS_LATENCIES, 0xe},
-	{SPD_BANK_DENSITY, 0x40},
-	{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff},
+	{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x40}, /* SPD_BANK_DENSITY */
+	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/
+	{SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
    {SPD_MEMORY_TYPE, 7},
-	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */
-	{SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */
    {SPD_NUM_BANKS_PER_SDRAM, 4},
-	{SPD_PRIMARY_SDRAM_WIDTH, 8},
    {SPD_NUM_DIMM_BANKS, 1},
-	{SPD_NUM_COLUMNS, 0xa},
+	{SPD_NUM_COLUMNS, 0x8},
    {SPD_NUM_ROWS, 13},
-	{SPD_REFRESH, 0x3a},
-	{SPD_SDRAM_CYCLE_TIME_2ND, 60},
-	{SPD_SDRAM_CYCLE_TIME_3RD, 75},
-	{SPD_tRAS, 40},
-	{SPD_tRCD, 15},
-	{SPD_tRFC, 70},
-	{SPD_tRP, 15},
-	{SPD_tRRD, 10},
+	{SPD_REFRESH, 0x82},
+	{SPD_SDRAM_CYCLE_TIME_2ND, 0x0},
+	{SPD_SDRAM_CYCLE_TIME_3RD, 0x0},
+	{SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, 0x2d}, /* SPD_tRAS */
+	{SPD_MIN_RAS_TO_CAS_DELAY, 0x58}, /* SPD_tRCD */
+	{SPD_tRFC, 0x4b},
+	{SPD_MIN_ROW_PRECHARGE_TIME, 0x58}, /* SPD_tRP */
+	{SPD_MIN_ROWACTIVE_TO_ROWACTIVE, 0x3c}, /* SPD_tRRD */
 };

/**
@@ -124,6 +141,8 @@
   */
 int main(void)
 {
+	void dumplxmsrs(void);
+
    u8 smb_devices[] =  {
    	DIMM0, DIMM1
    };
@@ -151,8 +170,11 @@
    sdram_enable(DIMM0, DIMM1);
    printk(BIOS_DEBUG, "done sdram enable\n");

+	dumplxmsrs();
    /* Check low memory */
-	ram_check(0x00000000, 640*1024);
+	/* passed. Don't bother any more */
+	/* Note that the range 0x87000 will fail; that's the stack! */
+	/*	ram_check(0x00000000, 640*1024);*/

printk(BIOS_DEBUG, "stage1 returns\n");
    return 0;
Index: LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c
===================================================================
--- LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c	(Revision 647)
+++ LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c	(Arbeitskopie)
@@ -35,6 +35,43 @@

u8 spd_read_byte(u16 device, u8 address);

+
+/** 
+ * Dump key MSR values for ram init. You can call this function and then use it to 
+ * compare to a fuctory bios setting.
+ * @param level printk level
+ */
+void dumplxmsrs(void)
+{
+	static unsigned long msrs[] = {
+        	MC_CF07_DATA, 
+        	MC_CF8F_DATA, 
+        	MC_CF1017_DATA, 
+        	GLCP_DELAY_CONTROLS, 
+        	MC_CFCLK_DBUG, 
+        	MC_CF_PMCTR,
+		GLCP_SYS_RSTPLL
+	};
+	static char *msrnames[] = {
+        	"MC_CF07_DATA", 
+        	"MC_CF8F_DATA", 
+        	"MC_CF1017_DATA", 
+        	"GLCP_DELAY_CONTROLS", 
+        	"MC_CFCLK_DBUG", 
+        	"MC_CF_PMCTR",
+		"PLL reg"
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(msrs); i++) {
+		struct msr msr;
+		msr = rdmsr(msrs[i]);
+		printk(BIOS_DEBUG, "%s (%lx): %x.%x\n",  msrnames[i], msrs[i],
+			msr.hi, msr.lo);
+	}
+
+}
+
 /**
  * Halt and Catch Fire. Print an error, then loop, sending NULLs on
  * serial port, to ensure the message is visible.
@@ -387,7 +424,7 @@
    	hlt();
    }

-	printk(BIOS_DEBUG, "Set cas latency to %x\n", spd_byte);
+	printk(BIOS_DEBUG, "Set CAS latency to %x\n", spd_byte);
    msr = rdmsr(MC_CF8F_DATA);
    msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
    msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;