On 11/01/2015 12:49 AM, Patrick Georgi wrote:
Just a note: the only reason why current Intel fares better
I didn't say Intel fares better. FSP is on my (rather long) hitlist, but that's not within the scope of this discussion.
7 min vs 20 min on empty ccache, and 2 min vs 6 min on primed ccache. Those are speedups of 2x to 3x.
Thank you for doing the measurements.
Thank you for creating the 'what-jenkins-does' make target.
Patch trains from google and other contributions to non-AGESA code gain a 2x to 3x speedup in server time, while users of AGESA can continue to contribute and work on the codebase.
... and diverge...
And that's expected. Convergence is a dream. AGESA boards use BuildOpts for configuration, and not much Kconfig/devicetree.cb, versus most other boards in the tree. Except for VX900 and sandybridge, every chipset implements its own SPD parsing routines. I can go on and on. Even within one branch, significant divergence exists, so non-divergence is a moot point.
Alex