Hi guys,
so together with a friend, I took the time to figure out how to enable the onboard Gigabit Ethernet on the Fujitsu(-Siemens) D1692 board, which is a minimally modified Tyan S2885.
(The D1692 boots fine with either the FSC PhoenixBIOS, the Tyan AMIBIOS or coreboot compiled for Tyan S2885!)
So, to have the BCM5703X appear on the PCI-X bus (as device 02:09.0), one has to:
on the W83627HF SuperIO: * enable the GPIO3 controller: device 9, reg 0x30, write 1 * set the second GPIO line as output: device 9, reg 0xf0, &= ~0x02 * set the second GPIO line to high: device 9, reg 0xf1, |= 0x02 * set the GPIO mux of that pin to GPIO: (any device), reg 0x29, |= 0x08
(this causes pin 72 on the W83627HF to go high)
that makes the BCM5703X appear, but it will behave very strangely - because it comes out of reset with the PCI-X bus running, so the strappings are wrong. to make it work correctly, finish with:
on the AMD 8131 PCI-X bridge, first PCI-X bus (device 00:0a.0) * trigger a secondary bus reset (SRST, PCI conf. 3B, bit 0x40)
and don't forget to end the reset :)
That will leave you with a properly PCI'ing BCM5703X. The remaining 10% that i haven't figured out is why it says
tg3 0000:02:09.0: enabling device (0000 -> 0002) tg3 0000:02:09.0: PCI->APIC IRQ transform: INT A -> IRQ 24 tg3 0000:02:09.0: phy probe failed, err -19 tg3 0000:02:09.0: Problem fetching invariants of chip, aborting
which seems due to the driver being unable to read the EEPROM (which contains a PHY identifier). but i'm not giving up this short off the finish line :)
Anyway, someone with the proper knowledge of where and how to add these bits, please do so! The FSC D1692 is fully working with the S2885 build, except for this small part!
-David, enjoying coreboot