On Thu, Jun 25, 2009 at 2:46 AM, Bao, Zheng Zheng.Bao@amd.com wrote:
amd_fam10_ht_sb_only.diff: I am not sure about this patch. Not sure to add signed-off-by line. Don't ack it before review it and say something.
My board is Fam10 + 1 HT SouthBridge. It is close to dbm690t. So I set HT_CHAIN_UNITID_BASE as 0 and HT_CHAIN_END_UNITID_BASE as 1, even though I don't know well what they actually are.
HT_CHAIN_UNITID_BASE and HT_CHAIN_END_UNITID_BASE change the way the chain is enumerated.
When HT devices are reset, their UNITID == 0 UNITID is very much like a pci device number. It is how the device claims configuration cycles. All devices implemented by a chip are offset by the unitid.
That means you can only send configuration cycles to the first device on the chain. After you check that device, if it has another HT link, you set the unitid to something larger than 0 (say 0x20) and then you can access the next device in the chain at unitid 0.
HT_CHAIN_END_UNITID_BASE is the unitid for the end of the chain.
For more information you'll have to read the code, because it seems to me that these values get used for multiple purposes.
Base on currently fam10
code, I have skip some code, otherwise the HT link can not be set up correctly. It is pretty like a workaround and my board can work in 1.8GHz (HT3). Doesn't the code in repository cover the mode of one HT processor + 1 HT SB device?
It does, as long as all the defines are correct.
To find out what the factory BIOS uses, you can look at lspci.
Thanks, Myles