Thanks, for the response.... Here's what I've got, what else do I miss here ?
I closed the patch
//#include <southbridge/intel/i82801gx/early_lpc.c> //#include <southbridge/intel/i82801gx/early_smbus.c> //#include <southbridge/intel/i82801gx/lpc.c>
and I got error : bianchi at ubuntu https://www.coreboot.org/mailman/listinfo/coreboot:~/coreboot$ make GEN generated/bootblock.ld CP bootblock/arch/x86/bootblock.ld LINK cbfs/fallback/bootblock.debug OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY bootblock.raw.bin CC romstage/mainboard/intel/i946gz/romstage.o LINK cbfs/fallback/romstage.debug build/romstage/mainboard/intel/i946gz/romstage.o: In function `mainboard_romstage_entry': /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214: undefined reference to `southbridge_detect_s3_resume' /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217: undefined reference to `enable_smbus' build/romstage/northbridge/intel/i945/raminit.o: In function `spd_read_byte': /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: more undefined references to `smbus_read_byte' follow src/arch/x86/Makefile.inc:264: recipe for target 'build/cbfs/fallback/romstage.debug' failed make: *** [build/cbfs/fallback/romstage.debug] Error 1
my Kconfig at /src/mainboard/intel/i946gz :
## ## This file is part of the coreboot project. ## ## Copyright (C) 2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## if BOARD_INTEL_I946GZ
config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC ##select NORTHBRIDGE_INTEL_I946GZ ##select NORTHBRIDGE_INTEL_SUBTYPE_I946GZ select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_ITE_IT8718F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 select CHANNEL_XOR_RANDOMIZATION select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_EDID
config MAINBOARD_DIR string default intel/i946gz
config MAINBOARD_PART_NUMBER string default "I946GZ"
config MMCONF_BASE_ADDRESS hex default 0xf0000000
config IRQ_SLOT_COUNT int default 18
config MAX_CPUS int default 1
endif # BOARD_INTEL_I946GZ
==== Including .c files is a bad idea. We did that before and still do in some places, but will get rid of it in the future hopefully. Also you are mixing romstage (early_*.c) and ramstage (lpc.c) code here.
I guess the remaining errors are caused by the mixing.
Hope that helps, Nico