I add the following code to sc_init() in southcluster.c to enable SERIRQ, and it works as expected when doing cold boot. With SERIRQ enabled, the uart in superio can function correctly, and I can login into the linux serial console. But after a reboot initiated from linux cmdline, the linux boot hang in getty serial(same as without SERIRQ enabled), only a power cycle can resolve the issue. I take the following code from coreboot-4.11 fsp-baytrail. I also tried the check_for_warm_reset() in bootblock.c to hardreset the machine, but the check condition in that procedure doesn't catch this situation, linux reset by default use keyboard controller seemingly.
u32 *oic = (u32 *)(ILB_BASE_ADDRESS + 0x60); u8 *serirq_cntl = (u8 *)(ILB_BASE_ADDRESS + 0x10);
/* Enable SERIRQ */ write32(oic, (read32(oic) | (1 << 12))); /* Enable continuous mode */ write8(serirq_cntl, (1 << 7));
On Thu, 04 Nov 2021 10:21:19 +0000 (UTC) Zhiwen Zheng zhiwen@40701.xyz wrote:
Now the raminit passed, thank you very much.
On Thu, 4 Nov 2021 08:56:49 +0000 Simon Newton simon.newton@gmail.com wrote:
Hi there Yes it does. Rename mrc.bin to mrc.elf
Regards
On Thu, 4 Nov 2021 at 08:45, Zhiwen Zheng zhiwen@40701.xyz wrote:
Hi,
I am trying to add a mainboard using celeron J1900 to coreboot-4.14, the serial console output stops after entering the MRC. The mrc.bin I used is extracted from Mrchromebox's roms for baytrail based chromebooks. _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
-- Kind Regards,
Simon Newton
E: Simon.newton@gmail.com
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org