Marc Jones Marc.Jones@amd.com writes:
I have thought about this a while back and have wanted to make a change. Disabling CAR should fixup the stack etc but for performance reasons we should setup/leave ROM and RAM caching enabled on the BSP. If you are interested in looking at that I think it would be great.
I considered that, but this being v2 I went with the unsophisticated approach; presuming it would be easier to debug and less intrusive a change. It might be wrong on that. of course, but when the naive modifications turned out to be sufficient I didn't investigate further. (I believe the time window where this is a problem is fairly small?)
How is the transition from CAR to regular cached DRAM done i v3? (I must admit to not being terribly hip with the v3 code base; is it approaching a stage where it might make sense to add something like the tyan s2912 port to it?)