Re: [coreboot] Update AMD Persimmon project to support Windows 7, XP, linux

[Marc Jones]

Hi Scott,
Thanks for this discussion.

On Thu, Apr 21, 2011 at 1:10 PM, Scott Duplichan  wrote:
> I have a set of AMD persimmon patches for improved OS support.
> The changes should easily port to ASRock E350M1 and AMD Inagua.
>
> These operating systems were tested and can install from a DVD and boot from hard disk:
> Windows 7 with SP1 and latest AMD video driver
> ubuntu-11.04-beta2-dvd-amd64.iso
> Windows Server 2003 x64 SP2
> Windows XP x64 SP2
>
> Live CD test only:
> linuxmint-9
> slax 6.12
> nimblex 2010 beta
>
> Here is a summary of the changes. Change #1 is essential, but it is a work around
> and not a true fix. Before submitting the patches, we should decide what to do
> about item #1. Here is a past discussion of the problem. While the past problem
> occurred only when a PCI video card was added, the current problem happens with
> no added cards:
> http://www.coreboot.org/pipermail/coreboot/2010-October/061320.html
>
> Here is the work around I am testing with. It limits device memory
> allocation to the area below MMCONF_BASE. The method works, but
> wastes address space:
> Index: src/devices/pci_device.c
> ===================================================================
> --- src/devices/pci_device.c  (revision 6483)
> +++ src/devices/pci_device.c  (working copy)
> @@ -259,6 +259,7 @@
>      if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
>         /* 32bit limit. */
>         resource->limit = 0xffffffffUL;
> resource->limit = CONFIG_MMCONF_BASE_ADDRESS - 1;
>
> } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
>         /* 1MB limit. */
>         resource->limit = 0x000fffffUL;
> Work around coreboot resource allocation problem that causes
>
> overlap of PCIe MMIO space and graphics MMIO space.

Why isn't this covered by the bus resource allocation for MMCONF? I
think that this should handle the situation. How does the overlap
happen?

static void cpu_bus_read_resources(device_t dev)
{
    printk(BIOS_DEBUG, "\nFam14h - cpu_bus_read_resources.\n");

#if CONFIG_MMCONF_SUPPORT
    struct resource *resource = new_resource(dev, 0xc0010058);
    resource->base = CONFIG_MMCONF_BASE_ADDRESS;
    resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
    resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
        IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
#endif
}

Thanks,
Marc
> Add device allocation for AP cores so that they will be reported and used by OS.
> Change cimx wrapper code so that OS shutdown function will work.
> Fix problems that cause incorrect programming and incorrect reporting of I/O APIC ID.
> Fix code that ignores MMCONF_BUS_NUMBER value and always uses 256.
> Change coreboot ACPI code to not report RTC as PIIX4 compatible.
> Add coreboot ACPI code to report PS/2 KB and mouse (ASRock only).
> Change coreboot ACPI code to report memory range A0000-Bffff as used.
> Change coreboot ACPI code to report proper FADT revision.
> Correct MP table reporting of APIC version.
> Program SB800 MiscCntrl earlier so first serial output is not garbled.
> Enable cache early to decrease coreboot execution time.
> Remove some unused HT code. Remove other unneeded code.
> Change seabios to use DMA instead of PIO for disk reads.
>
> Thanks,
> Scott