Re: [coreboot] [PATCH] move PHY fine tune to devicetree.cb

[Stefan Reinauer]

On 8/22/10 10:37 PM, Rudolf Marek wrote:
> Index: src/mainboard/amd/mahogany/devicetree.cb
>
> --- src/mainboard/amd/mahogany/devicetree.cb.orig	2010-08-22 11:54:20.000000000 +0200
> +++ src/mainboard/amd/mahogany/devicetree.cb	2010-08-22 12:12:45.000000000 +0200
> @@ -110,6 +110,19 @@
>    				register "sata0_enable" = "1"
>    				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
>    				register "hda_viddid" = "0x10ec0882"
> 			# SATA PHY fine tune, depends on PCB layout!
> 			register "sphy15_p0" = "0x01b48017"
> 			register "sphy15_p1" = "0x01b48019"
> 			register "sphy15_p2" = "0x01b48016"
> 			register "sphy15_p3" = "0x01b48016"
> 			register "sphy15_p4" = "0x01b48016"
> 			register "sphy15_p5" = "0x01b48016"
> 			register "sphy30_p0" = "0xa09a"
> 			register "sphy30_p1" = "0xa09f"
> 			register "sphy30_p2" = "0xa07a"
> 			register "sphy30_p3" = "0xa07a"
> 			register "sphy30_p4" = "0xa07a"
> 			register "sphy30_p5" = "0xa07a"
> 	end	#southbridge/amd/sb700
> end #  device pci 18.0

Shouldn't such values rather go into the mainboard specific code (ie an
array in mainboard,c) instead of the device tree?