# lspci -xxxnns 0:0.0 00:00.0 Host bridge [0600]: Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub [8086:2770] 00: 86 80 70 27 06 00 90 20 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 53 4e 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 90 d1 fe 01 40 d1 fe 03 00 00 f0 01 80 d1 fe 50: 00 00 02 00 03 00 00 00 00 00 00 00 00 00 00 00 60: 01 30 d1 fe 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 11 11 11 11 33 33 00 ff 03 00 00 40 1a 39 00 a0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 91 00 00 00 e0: 09 00 09 71 cb e1 9b 98 07 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00
It is the byte at offset 8 makes me questioning. It is the revision identification register. This machine has a 945PL nb. According to Intel's doc(945x specification update 307503-010), the register should have a value of 82. Am I making mistake?
BTW, is the 0xe7 byte, with a value of '98', the same byte as the 'reg8' in the following excerpt of v3/northbridge/intel/i945/stage1.c?
static void i945_detect_chipset(void) { u8 reg8;
printk(BIOS_INFO, "\n"); reg8 = (pci_conf1_read_config8(PCI_BDF(0, 0x00, 0), 0xe7) & 0x70) >> 4;
yu ning