Author: stepan Date: 2009-09-23 20:51:03 +0200 (Wed, 23 Sep 2009) New Revision: 4661
Added: trunk/coreboot-v2/src/lib/generic_dump_spd.c trunk/coreboot-v2/src/lib/generic_sdram.c trunk/coreboot-v2/src/lib/ramtest.c Removed: trunk/coreboot-v2/src/ram/ trunk/coreboot-v2/src/sdram/ Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/auto.c trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/auto.c trunk/coreboot-v2/src/mainboard/amd/db800/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/amd/norwich/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/amd/rumba/auto.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/auto.c trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/asus/mew-am/auto.c trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c trunk/coreboot-v2/src/mainboard/asus/p2b-d/auto.c trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c trunk/coreboot-v2/src/mainboard/axus/tc320/auto.c trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c trunk/coreboot-v2/src/mainboard/bcom/winnet100/auto.c trunk/coreboot-v2/src/mainboard/bcom/winnetp680/auto.c trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/auto.c trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/auto.c trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/iei/juki-511p/auto.c trunk/coreboot-v2/src/mainboard/iei/nova4899r/auto.c trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c trunk/coreboot-v2/src/mainboard/intel/truxton/auto.c trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/jetway/j7f24/auto.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c trunk/coreboot-v2/src/mainboard/lippert/frontrunner/auto.c trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/mitac/6513wu/auto.c trunk/coreboot-v2/src/mainboard/msi/ms6119/auto.c trunk/coreboot-v2/src/mainboard/msi/ms6147/auto.c trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c trunk/coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/msi/ms9282/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/nec/powermate2000/auto.c trunk/coreboot-v2/src/mainboard/newisys/khepri/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/olpc/btest/auto.c trunk/coreboot-v2/src/mainboard/olpc/rev_a/auto.c trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/auto.c trunk/coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/auto.c trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/auto.c trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.c trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/auto.c trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/auto.c trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/technologic/ts5300/auto.c trunk/coreboot-v2/src/mainboard/televideo/tc7020/auto.c trunk/coreboot-v2/src/mainboard/thomson/ip1000/auto.c trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c trunk/coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2885/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s4882/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/via/epia-n/auto.c trunk/coreboot-v2/src/mainboard/via/epia/auto.c trunk/coreboot-v2/src/mainboard/via/pc2500e/auto.c trunk/coreboot-v2/src/mainboard/via/vt8454c/auto.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c trunk/coreboot-v2/src/northbridge/intel/e7520/raminit_test.c trunk/coreboot-v2/src/northbridge/intel/e7525/raminit_test.c trunk/coreboot-v2/src/northbridge/via/vx800/examples/cache_as_ram_auto.c Log: simplify source tree hierarchy: move files from sdram/ and ram/ to lib/ It's only three files. Also fix up all the paths (Gotta love included C files)
Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Ronald G. Minnich rminnich@gmail.com
Copied: trunk/coreboot-v2/src/lib/generic_dump_spd.c (from rev 4660, trunk/coreboot-v2/src/sdram/generic_dump_spd.c) =================================================================== --- trunk/coreboot-v2/src/lib/generic_dump_spd.c (rev 0) +++ trunk/coreboot-v2/src/lib/generic_dump_spd.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -0,0 +1,93 @@ +/* + * This code is derived from the Opteron boards' debug.c. + * It should go away either there or here, depending what fits better. + */ + +static void dump_spd_registers(const struct mem_controller *ctrl) +{ + int i; + print_debug("\r\n"); + for(i = 0; i < 4; i++) { + unsigned device; + device = ctrl->channel0[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = spd_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + device = ctrl->channel1[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".1: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = spd_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + } +} + +#if 0 +void dump_spd_registers(void) +{ + unsigned device; + device = SMBUS_MEM_DEVICE_START; + printk_debug("\n"); + while(device <= SMBUS_MEM_DEVICE_END) { + int status = 0; + int i; + printk_debug("dimm %02x", device); + for(i = 0; (i < 256) && (status == 0); i++) { + unsigned char byte; + if ((i % 20) == 0) { + printk_debug("\n%3d: ", i); + } + status = smbus_read_byte(device, i, &byte); + if (status != 0) { + printk_debug("bad device\n"); + continue; + } + printk_debug("%02x ", byte); + } + device += SMBUS_MEM_DEVICE_INC; + printk_debug("\n"); + } +} +#endif
Copied: trunk/coreboot-v2/src/lib/generic_sdram.c (from rev 4660, trunk/coreboot-v2/src/sdram/generic_sdram.c) =================================================================== --- trunk/coreboot-v2/src/lib/generic_sdram.c (rev 0) +++ trunk/coreboot-v2/src/lib/generic_sdram.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -0,0 +1,67 @@ + +#ifndef RAMINIT_SYSINFO + #define RAMINIT_SYSINFO 0 +#endif + +static inline void print_debug_sdram_8(const char *strval, uint32_t val) +{ +#if CONFIG_USE_INIT + printk_debug("%s%02x\r\n", strval, val); +#else + print_debug(strval); print_debug_hex8(val); print_debug("\r\n"); +#endif +} + +void sdram_no_memory(void) +{ + print_err("No memory!!\r\n"); + while(1) { + hlt(); + } +} + +/* Setup SDRAM */ +#if RAMINIT_SYSINFO == 1 +void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo) +#else +void sdram_initialize(int controllers, const struct mem_controller *ctrl) +#endif +{ + int i; + /* Set the registers we can set once to reasonable values */ + for(i = 0; i < controllers; i++) { + print_debug_sdram_8("Ram1.",i); + + #if RAMINIT_SYSINFO == 1 + sdram_set_registers(ctrl + i , sysinfo); + #else + sdram_set_registers(ctrl + i); + #endif + } + + /* Now setup those things we can auto detect */ + for(i = 0; i < controllers; i++) { + print_debug_sdram_8("Ram2.",i); + + #if RAMINIT_SYSINFO == 1 + sdram_set_spd_registers(ctrl + i , sysinfo); + #else + sdram_set_spd_registers(ctrl + i); + #endif + + } + + /* Now that everything is setup enable the SDRAM. + * Some chipsets do the work for us while on others + * we need to it by hand. + */ + print_debug("Ram3\r\n"); + + #if RAMINIT_SYSINFO == 1 + sdram_enable(controllers, ctrl, sysinfo); + #else + sdram_enable(controllers, ctrl); + #endif + + print_debug("Ram4\r\n"); +}
Copied: trunk/coreboot-v2/src/lib/ramtest.c (from rev 4660, trunk/coreboot-v2/src/ram/ramtest.c) =================================================================== --- trunk/coreboot-v2/src/lib/ramtest.c (rev 0) +++ trunk/coreboot-v2/src/lib/ramtest.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -0,0 +1,161 @@ +static void write_phys(unsigned long addr, unsigned long value) +{ +#if CONFIG_HAVE_MOVNTI + asm volatile( + "movnti %1, (%0)" + : /* outputs */ + : "r" (addr), "r" (value) /* inputs */ +#ifndef __GNUC__ + : /* clobbers */ +#endif + ); +#else + volatile unsigned long *ptr; + ptr = (void *)addr; + *ptr = value; +#endif +} + +static unsigned long read_phys(unsigned long addr) +{ + volatile unsigned long *ptr; + ptr = (void *)addr; + return *ptr; +} + +static void ram_fill(unsigned long start, unsigned long stop) +{ + unsigned long addr; + /* + * Fill. + */ +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("DRAM fill: 0x%08x-0x%08x\r\n", start, stop); +#else + print_debug("DRAM fill: "); + print_debug_hex32(start); + print_debug("-"); + print_debug_hex32(stop); + print_debug("\r\n"); +#endif + for(addr = start; addr < stop ; addr += 4) { + /* Display address being filled */ + if (!(addr & 0xfffff)) { +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("%08x \r", addr); +#else + print_debug_hex32(addr); + print_debug(" \r"); +#endif + } + write_phys(addr, addr); + }; + /* Display final address */ +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("%08x\r\nDRAM filled\r\n", addr); +#else + print_debug_hex32(addr); + print_debug("\r\nDRAM filled\r\n"); +#endif +} + +static void ram_verify(unsigned long start, unsigned long stop) +{ + unsigned long addr; + int i = 0; + /* + * Verify. + */ +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("DRAM verify: 0x%08x-0x%08x\r\n", start, stop); +#else + print_debug("DRAM verify: "); + print_debug_hex32(start); + print_debug_char('-'); + print_debug_hex32(stop); + print_debug("\r\n"); +#endif + for(addr = start; addr < stop ; addr += 4) { + unsigned long value; + /* Display address being tested */ + if (!(addr & 0xfffff)) { +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("%08x \r", addr); +#else + print_debug_hex32(addr); + print_debug(" \r"); +#endif + } + value = read_phys(addr); + if (value != addr) { + /* Display address with error */ +#if CONFIG_USE_PRINTK_IN_CAR + printk_err("Fail: @0x%08x Read value=0x%08x\r\n", addr, value); +#else + print_err("Fail: @0x"); + print_err_hex32(addr); + print_err(" Read value=0x"); + print_err_hex32(value); + print_err("\r\n"); +#endif + i++; + if(i>256) { +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("Aborting.\n\r"); +#else + print_debug("Aborting.\n\r"); +#endif + break; + } + } + } + /* Display final address */ +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("%08x", addr); +#else + print_debug_hex32(addr); +#endif + + if (i) { +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("\r\nDRAM did _NOT_ verify!\r\n"); +#else + print_debug("\r\nDRAM did _NOT_ verify!\r\n"); +#endif + die("DRAM ERROR"); + } + else { +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("\r\nDRAM range verified.\r\n"); +#else + print_debug("\r\nDRAM range verified.\r\n"); +#endif + } +} + + +void ram_check(unsigned long start, unsigned long stop) +{ + /* + * This is much more of a "Is my DRAM properly configured?" + * test than a "Is my DRAM faulty?" test. Not all bits + * are tested. -Tyson + */ +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("Testing DRAM : %08x - %08x\r\n", start, stop); +#else + print_debug("Testing DRAM : "); + print_debug_hex32(start); + print_debug("-"); + print_debug_hex32(stop); + print_debug("\r\n"); +#endif + ram_fill(start, stop); + ram_verify(start, stop); +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("Done.\r\n"); +#else + print_debug("Done.\r\n"); +#endif +} +
Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -27,7 +27,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977f/w83977f_early_serial.c"
Modified: trunk/coreboot-v2/src/mainboard/amd/db800/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/amd/db800/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -27,7 +27,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> @@ -55,7 +55,7 @@ #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c"
Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -88,7 +88,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -27,7 +27,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> @@ -53,7 +53,7 @@ #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c"
Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -82,7 +82,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -8,7 +8,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" @@ -93,7 +93,7 @@ }
#include "northbridge/amd/gx2/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#define PLLMSRhi 0x00001490 #define PLLMSRlo 0x02000030
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -126,7 +126,7 @@
#include "northbridge/amd/amdk8/raminit_f.c"
-#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* tyan does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -63,7 +63,7 @@ #if (CONFIG_USE_FAILOVER_IMAGE == 0) #include "arch/i386/lib/console.c" #include "pc80/serial.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h"
Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -12,7 +12,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -78,7 +78,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1
Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> @@ -72,7 +72,7 @@ #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c"
Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -27,7 +27,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" #include "superio/nsc/pc87351/pc87351_early_serial.c"
Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -28,7 +28,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc87351/pc87351_early_serial.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -58,7 +58,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -92,7 +92,7 @@ }
#include "northbridge/amd/amdk8/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup.c" #include "cpu/amd/car/copy_and_run.c"
Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -113,7 +113,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/via/k8t890/k8t890_early_car.c" #include "cpu/amd/car/copy_and_run.c"
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -100,7 +100,7 @@ #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c"
Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-d/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -30,7 +30,7 @@ #include <cpu/x86/lapic.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -30,7 +30,7 @@ #include <cpu/x86/lapic.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -28,7 +28,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnet100/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -28,7 +28,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -30,7 +30,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -21,7 +21,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#if 0 static void post_code(uint8_t value) { @@ -89,7 +89,7 @@
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* tyan does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -10,7 +10,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" @@ -71,7 +71,7 @@ }
#include "northbridge/intel/e7520/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -14,7 +14,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c" #include "northbridge/intel/i855pm/raminit.h"
@@ -59,7 +59,7 @@
#include "northbridge/intel/i855pm/raminit.c" #include "northbridge/intel/i855pm/reset_test.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
static void main(unsigned long bist) {
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -9,7 +9,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "cpu/x86/bist.h" //#include "lib/delay.c"
@@ -74,7 +74,7 @@ // return smbus_read_byte(device, address); }
-//#include "sdram/generic_sdram.c" +//#include "lib/generic_sdram.c"
static inline void dumpmem(void){ int i, j;
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -8,7 +8,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" //#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" @@ -82,7 +82,7 @@ }
#include "northbridge/amd/lx/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* CPU and GLIU mult/div */ #define PLLMSRhi 0x0000039C
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -8,7 +8,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> @@ -35,7 +35,7 @@ #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c"
Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -9,7 +9,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" //#include "southbridge/intel/i440bx/i440bx_early_smbus.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" //#include "northbridge/intel/i440bx/raminit.h"
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -65,7 +65,7 @@ #include "southbridge/sis/sis966/sis966_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" #endif -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
@@ -121,7 +121,7 @@
#include "northbridge/amd/amdk8/raminit_f.c"
-#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -63,7 +63,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" #endif -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
@@ -119,7 +119,7 @@
#include "northbridge/amd/amdk8/raminit_f.c"
-#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -65,7 +65,7 @@ #if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
@@ -128,7 +128,7 @@
#include "northbridge/amd/amdk8/raminit_f.c"
-#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
//#include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -13,7 +13,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -75,7 +75,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1
Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -13,7 +13,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -75,7 +75,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1
Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -28,7 +28,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "superio/winbond/w83977f/w83977f_early_serial.c" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c"
Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -28,7 +28,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -27,7 +27,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> @@ -60,7 +60,7 @@ #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c"
Modified: trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -38,7 +38,7 @@ #include "arch/i386/lib/console.c" #include <cpu/x86/bist.h>
-#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" #include "reset.c" @@ -117,7 +117,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "northbridge/intel/i3100/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "northbridge/intel/i3100/reset_test.c" #include "debug.c"
Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -10,7 +10,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" @@ -49,7 +49,7 @@ }
#include "northbridge/intel/e7520/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "debug.c"
Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -30,7 +30,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" #include "northbridge/intel/i3100/raminit.h" @@ -57,7 +57,7 @@ }
#include "northbridge/intel/i3100/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "../jarrell/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -31,7 +31,7 @@ #include "pc80/serial.c" #include "pc80/udelay_io.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" @@ -57,7 +57,7 @@ }
#include "northbridge/intel/i3100/raminit_ep80579.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "../../intel/jarrell/debug.c"
/* #define TRUXTON_DEBUG */
Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -12,7 +12,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82801ca/i82801ca_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "cpu/x86/lapic/boot_cpu.c" @@ -41,7 +41,7 @@
#include "northbridge/intel/e7501/raminit.c" #include "northbridge/intel/e7501/reset_test.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
// This function MUST appear last (ROMCC limitation)
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -106,8 +106,8 @@
#include "northbridge/amd/amdk8/raminit.c"
-#include "sdram/generic_sdram.c" -#include "ram/ramtest.c" +#include "lib/generic_sdram.c" +#include "lib/ramtest.c"
/* tyan does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -106,8 +106,8 @@
#include "northbridge/amd/amdk8/raminit.c"
-#include "sdram/generic_sdram.c" -#include "ram/ramtest.c" +#include "lib/generic_sdram.c" +#include "lib/ramtest.c"
/* tyan does not want the default */ #include "northbridge/amd/amdk8/resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -106,8 +106,8 @@
#include "northbridge/amd/amdk8/raminit.c"
-#include "sdram/generic_sdram.c" -#include "ram/ramtest.c" +#include "lib/generic_sdram.c" +#include "lib/ramtest.c"
/* tyan does not want the default */ #include "northbridge/amd/amdk8/resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -30,7 +30,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -45,7 +45,7 @@ #include "pc80/usbdebug_direct_serial.c" #endif
-#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "reset.c" #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -8,7 +8,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" @@ -40,7 +40,7 @@ }
#include "northbridge/amd/gx2/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#define PLLMSRhi 0x00000226 #define PLLMSRlo 0x00000008
Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -31,7 +31,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> @@ -61,7 +61,7 @@ #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c"
Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -32,7 +32,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> @@ -123,7 +123,7 @@ #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c"
Modified: trunk/coreboot-v2/src/mainboard/mitac/6513wu/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/mitac/6513wu/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6119/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/msi/ms6119/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -60,7 +60,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -94,7 +94,7 @@ }
#include "northbridge/amd/amdk8/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup_car.c" #include "cpu/amd/car/copy_and_run.c"
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -68,7 +68,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" #endif -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -107,7 +107,7 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c"
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -130,7 +130,7 @@
#include "northbridge/amd/amdk8/raminit_f.c"
-#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* msi does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -111,7 +111,7 @@ #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* msi does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/nec/powermate2000/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -17,7 +17,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#if 0 static void post_code(uint8_t value) { @@ -90,7 +90,7 @@
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* newisys khepri does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -63,7 +63,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" #endif -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
@@ -118,7 +118,7 @@
#include "northbridge/amd/amdk8/raminit_f.c"
-#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/olpc/btest/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/btest/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/olpc/btest/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -8,7 +8,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" @@ -129,7 +129,7 @@ }
#include "northbridge/amd/gx2/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#define PLLMSRhi 0x00001490 #define PLLMSRlo 0x02000030
Modified: trunk/coreboot-v2/src/mainboard/olpc/rev_a/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/rev_a/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -8,7 +8,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" @@ -129,7 +129,7 @@ }
#include "northbridge/amd/gx2/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#define PLLMSRhi 0x00001490 #define PLLMSRlo 0x02000030
Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -28,7 +28,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> @@ -115,7 +115,7 @@ #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c"
Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -30,7 +30,7 @@ #include "pc80/serial.c" #include "pc80/udelay_io.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" @@ -69,7 +69,7 @@ }
#include "northbridge/intel/i82830/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/** * The AC'97 Audio Controller I/O space registers are read only by default
Modified: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -24,7 +24,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -83,7 +83,7 @@
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* tyan does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -56,7 +56,7 @@ #if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
@@ -169,7 +169,7 @@
#include "northbridge/amd/amdk8/raminit_f.c"
-#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -60,7 +60,7 @@ #if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
@@ -116,7 +116,7 @@
#include "northbridge/amd/amdk8/raminit_f.c"
-#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -10,7 +10,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" #include "northbridge/intel/e7525/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" @@ -52,7 +52,7 @@ }
#include "northbridge/intel/e7525/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
static void main(unsigned long bist)
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -10,7 +10,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" @@ -70,7 +70,7 @@ }
#include "northbridge/intel/e7520/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
static void main(unsigned long bist)
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -10,7 +10,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" @@ -70,7 +70,7 @@ }
#include "northbridge/intel/e7520/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
static void main(unsigned long bist)
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -10,7 +10,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" @@ -70,7 +70,7 @@ }
#include "northbridge/intel/e7520/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
static void main(unsigned long bist)
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -10,7 +10,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" @@ -71,7 +71,7 @@ }
#include "northbridge/intel/e7520/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
static void main(unsigned long bist)
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -10,7 +10,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" @@ -71,7 +71,7 @@ }
#include "northbridge/intel/e7520/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
static void main(unsigned long bist)
Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -88,7 +88,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/ts5300/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -15,7 +15,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "cpu/x86/bist.h"
#define TS5300_LED_OFF outb((inb(0x77)&0xfe), 0x77)
Modified: trunk/coreboot-v2/src/mainboard/televideo/tc7020/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -28,7 +28,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -30,7 +30,7 @@ #include "pc80/serial.c" #include "pc80/udelay_io.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" @@ -69,7 +69,7 @@ }
#include "northbridge/intel/i82830/raminit.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/** * The AC'97 Audio Controller I/O space registers are read only by default
Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -12,7 +12,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#if 0 static void post_code(uint8_t value) { @@ -74,7 +74,7 @@
#include "northbridge/intel/e7501/raminit.c" #include "northbridge/intel/e7501/reset_test.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#include "cpu/x86/car/copy_and_run.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -13,7 +13,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#if 0 static void post_code(uint8_t value) { @@ -80,7 +80,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -13,7 +13,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -70,7 +70,7 @@
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c" #include "northbridge/amd/amdk8/resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -13,7 +13,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> @@ -72,7 +72,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -18,7 +18,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#if 0 static void post_code(uint8_t value) { @@ -87,7 +87,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -13,7 +13,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -71,7 +71,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -12,7 +12,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#if 0 static void post_code(uint8_t value) { @@ -81,7 +81,7 @@
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* tyan does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -19,7 +19,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
@@ -60,7 +60,7 @@
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* tyan does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -12,7 +12,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
@@ -56,7 +56,7 @@
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* tyan does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -24,7 +24,7 @@ #if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
@@ -87,7 +87,7 @@
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* tyan does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -63,7 +63,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" #endif -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
@@ -118,7 +118,7 @@
#include "northbridge/amd/amdk8/raminit_f.c"
-#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
#include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -60,7 +60,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" #endif -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -13,7 +13,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -85,7 +85,7 @@
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* tyan does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -12,7 +12,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -93,7 +93,7 @@
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" +#include "lib/generic_sdram.c"
/* tyan does not want the default */ #include "resourcemap.c"
Modified: trunk/coreboot-v2/src/mainboard/via/epia/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/via/epia/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -9,7 +9,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/via/vt8601/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -37,7 +37,7 @@
#include "northbridge/via/vt8601/raminit.c" /* - #include "sdram/generic_sdram.c" + #include "lib/generic_sdram.c" */
static void enable_mainboard_devices(void)
Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -30,7 +30,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -13,7 +13,7 @@ #include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/via/vt8623/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -36,7 +36,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/via/vx800/vx800.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-n/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/via/epia-n/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -30,7 +30,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/via/cn400/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/mainboard/via/pc2500e/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/pc2500e/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/via/pc2500e/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -31,7 +31,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/mainboard/via/vt8454c/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/vt8454c/auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/mainboard/via/vt8454c/auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -30,7 +30,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/via/cx700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -305,7 +305,7 @@ }
#include "raminit.c" -#include "../../../sdram/generic_sdram.c" +#include "../../../lib/generic_sdram.c"
#define FIRST_CPU 1 #define SECOND_CPU 1
Modified: trunk/coreboot-v2/src/northbridge/intel/e7520/raminit_test.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7520/raminit_test.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/northbridge/intel/e7520/raminit_test.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -305,7 +305,7 @@ }
#include "raminit.c" -#include "../../../sdram/generic_sdram.c" +#include "../../../lib/generic_sdram.c"
#define FIRST_CPU 1 #define SECOND_CPU 1
Modified: trunk/coreboot-v2/src/northbridge/intel/e7525/raminit_test.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7525/raminit_test.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/northbridge/intel/e7525/raminit_test.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -276,7 +276,7 @@ }
#include "raminit.c" -#include "../../../sdram/generic_sdram.c" +#include "../../../lib/generic_sdram.c"
#define FIRST_CPU 1 #define SECOND_CPU 1
Modified: trunk/coreboot-v2/src/northbridge/via/vx800/examples/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vx800/examples/cache_as_ram_auto.c 2009-09-23 17:59:56 UTC (rev 4660) +++ trunk/coreboot-v2/src/northbridge/via/vx800/examples/cache_as_ram_auto.c 2009-09-23 18:51:03 UTC (rev 4661) @@ -32,7 +32,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" +#include "lib/ramtest.c" #include "northbridge/via/vx800/vx800.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"