On Wednesday, May 7, 2003, at 03:06 PM, ron minnich wrote:
what is your southbridge part? can you look at the part directly?
So I have the datasheet for the 5595 now (found using google so not sure whether I should send it to you) um either way to enable flash they talk about using the
"address and data port, i.e. Port 70h and 71h, respectively. The access control with which the three portions of registers can be appropriately addressed are stored in PCI-ISA: 45h[3] (EXTEND_EN bit) and PCI-ISA: 45h[1](APCREG_EN bit)." but in the sis530 docs I get this for registers 70h:
"Register 70h to register 76h define the attribute of the Shadow RAM from 640 KBytes to 1 MBytes. All of the registers 70h to 75h are defined as below, and each register defines the corresponding memory segment's attribute which are listed in the following table. REGISTER DEFINED RANGE REGISTER DEFINED RANGE Register 70h bits 7:5 0C0000h-0C3FFFh Register 73h bits 7:5 0D8000h-0DBFFFh"
so I'm not sure how to set that in the 5595..? There must be some way through the pci bridge I think, but don't really know what I'm doing... so some pointers (or even pointers to some docs on how things work) would be great.
Register 45h (on the 5595) controls the flash writability. But on the sis530 45h is "IDE Secondary Channel/Master Drive Data Active Time Control" so again it is a matter of knowing how to communicate with the 5595 instead of the main chipset.
Now this is all great and what not, but I'm confused. We're having problems detecting the flash, not writing to it. So I'm not sure how this will help. As well in the flash_rom sources the enable_sis is never called.
In going over the sources to devbios and the flash_rom, I realize that I don't know anything much about the pci/isa bridges and such...
So basically I'm wondering what the next step is. 1) Does the write enable bit help with detecting? 2) Where do I get docs about how the pci & isa communication happens? 2a) do I need those docs?
that's about it...