Peter Stuge wrote:
Hi,
On Mon, Jul 02, 2007 at 04:17:51PM +0700, Darmawan Salihun wrote:
The diff for the latest winflashrom code is attached.
The diff is reversed, so a bit hard to read. Please do svn diff -r1:HEAD next time.
Also, instead of commenting out non-Windows code and adding new Windows-only code, please suggest good ways to abstract the code.
There are a few things that need to be abstracted in order to unify the Unix-based code and the Windows version. After thinking about the solution for a while I found that it maybe better if I made a kind of abstraction layer for the "incompatible" parts that only impose minor changes to the current flashrom code base prior to doing a "redesign" to the overall source code to address the Windows-*NIX "incompatibilities". This is only a temporary workaround. The most obvious parts are:
1. Libpci abstraction for Windows. In this case the libpci logic in the flashrom code base need not be changed. I will make a "libpci for Windows" that doesn't change the logic within the current flashrom code. Even after the redesign, we might choose to preserve this part.
2. Direct I/O access abstraction. I think, in the short term, I will just provide a simple direct I/O "compatibility layer" for inX,outX family of functions in the winflashrom.
3. File I/O abstraction. We might need this because fopen(..) behaves not exactly the same in Windows and *NIX.
Remember that this is only a short term solution. Anyway, do you think it's good to make a branch for the current flashrom code in order to develop the unified (redesigned) flashrom that will host a single code base for both the *NIX version and winflashrom? I mean the branch will be merged into the trunk once we have a well tested unified version of flashrom/winflashrom.
Another note that I have difficulty in limiting the direct I/O access in the current driver because I don't know exactly which port to give access to and which one to block. Below is what I've found from the current flashrom code so far. I/O port usage:
0x2E (Winbond W836_INDEX port) 0x2F (Winbond W836_DATA port) 0x4E 0x4F 0xCD6 0xCD7 0xCFC - 0xCFF (PCI I/O port on x86) 0xC6F a "base + 0x4D" in Via Epia motherboard 0xE1 0xE800 (what port is this? ) 0xE801 0xE802 0xE803 0xE804 0xE807 0xEB 0xFF
I couldn't conclude the the I/O port ranges to open from the port list above because there is still unknown (I think it's dynamically relocatable) I/O port such as the one used by EPIA board. Any explanation on this issue?
That's all for now.
Regards, Darmawan Salihun