Sven Schnelle (svens@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1202
-gerrit
commit 10f661844f6205454a51a234e865424e3726f24f Author: Sven Schnelle svens@stackframe.org Date: Thu Jul 5 12:02:55 2012 +0200
Add Fujitsu Siemens TX200 S3
Change-Id: I4a8e906b72dc4270976096ccb74920288ae4f026 Signed-off-by: Sven Schnelle svens@stackframe.org --- src/mainboard/Kconfig | 3 + src/mainboard/fsc/Kconfig | 16 +++ src/mainboard/fsc/tx200s3/Kconfig | 45 +++++++ src/mainboard/fsc/tx200s3/chip.h | 21 +++ src/mainboard/fsc/tx200s3/cmos.layout | 142 ++++++++++++++++++++ src/mainboard/fsc/tx200s3/devicetree.cb | 145 +++++++++++++++++++++ src/mainboard/fsc/tx200s3/irq_tables.c | 57 ++++++++ src/mainboard/fsc/tx200s3/mainboard.c | 117 +++++++++++++++++ src/mainboard/fsc/tx200s3/mptable.c | 68 ++++++++++ src/mainboard/fsc/tx200s3/romstage.c | 214 +++++++++++++++++++++++++++++++ 10 files changed, 828 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index b53b0e7..7abafc0 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -52,6 +52,8 @@ config VENDOR_ECS bool "ECS" config VENDOR_EMULATION bool "Emulation" +config VENDOR_FSC + bool "Fujitsu Siemens Computer(FSC)" config VENDOR_GETAC bool "Getac" config VENDOR_GIGABYTE @@ -153,6 +155,7 @@ source "src/mainboard/digitallogic/Kconfig" source "src/mainboard/eaglelion/Kconfig" source "src/mainboard/ecs/Kconfig" source "src/mainboard/emulation/Kconfig" +source "src/mainboard/fsc/Kconfig" source "src/mainboard/getac/Kconfig" source "src/mainboard/gigabyte/Kconfig" source "src/mainboard/hp/Kconfig" diff --git a/src/mainboard/fsc/Kconfig b/src/mainboard/fsc/Kconfig new file mode 100644 index 0000000..aa5ca11 --- /dev/null +++ b/src/mainboard/fsc/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_FSC + +choice + prompt "Mainboard model" + +config BOARD_FSC_TX200S3 + bool "TX200 S3" +endchoice + +source "src/mainboard/fsc/tx200s3/Kconfig" + +config MAINBOARD_VENDOR + string + default "FSC (Fujitsu Siemens Computer)" + +endif # VENDOR_FSC diff --git a/src/mainboard/fsc/tx200s3/Kconfig b/src/mainboard/fsc/tx200s3/Kconfig new file mode 100644 index 0000000..71d6b56 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/Kconfig @@ -0,0 +1,45 @@ +if BOARD_FSC_TX200S3 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA771 + select SOUTHBRIDGE_INTEL_I3100 + select NORTHBRIDGE_INTEL_I5000 + select SUPERIO_SMSC_SMSCSUPERIO + select MMCONF_SUPPORT + select BOARD_ROMSIZE_KB_512 + select HAVE_MP_TABLE + select HAVE_PIRQ_TABLE + select IPMI_KCS + select DRIVERS_GENERIC_IOAPIC + +config MAINBOARD_DIR + string + default fsc/tx200s3 + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +config MAINBOARD_PART_NUMBER + string + default "TX200 S3" + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config IRQ_SLOT_COUNT + int + default 48 + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/fsc/tx200s3/chip.h b/src/mainboard/fsc/tx200s3/chip.h new file mode 100644 index 0000000..70f9bb4 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/fsc/tx200s3/cmos.layout b/src/mainboard/fsc/tx200s3/cmos.layout new file mode 100644 index 0000000..29e78ad --- /dev/null +++ b/src/mainboard/fsc/tx200s3/cmos.layout @@ -0,0 +1,142 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/fsc/tx200s3/devicetree.cb b/src/mainboard/fsc/tx200s3/devicetree.cb new file mode 100644 index 0000000..81ff95d --- /dev/null +++ b/src/mainboard/fsc/tx200s3/devicetree.cb @@ -0,0 +1,145 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle svens@stackframe.org +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i5000 + + device lapic_cluster 0 on + chip cpu/intel/socket_LGA771 + device lapic 0 on end + end + end + device pci_domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x15d9 0x2017 + end + + device pci 02.0 on # PCI Express x8 Port 2-3 + device pci 00.0 on # PCI Express Upstream Port + device pci 00.0 on # PCI Express Downstream Port E1 + device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A + # PCI slot + device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B + # PCI slot + end + end + + end + device pci 02.0 on # PCI Express Downstream Port E3 + device pci 00.0 on end # e1000 #1 + device pci 00.1 on end # e1000 #2 + end + end + device pci 00.3 on # PCI Express to PCI-X Bridge + # PCI-X Slot + end + end + + device pci 03.0 on end + device pci 10.0 on end # FBD + device pci 10.1 on end # FBD + device pci 10.2 on end # FBD + device pci 11.0 on end # FBD reserved + device pci 13.0 on end # FBD reserved + device pci 15.0 on end # FBD + device pci 16.0 on end # FBD + + chip southbridge/intel/i3100 + register "pirq_a_d" = "0x0b0b0b0b" + register "pirq_e_h" = "0x80808080" + register "sata_ports_implemented" = "0x3f" + + device pci 1c.0 on end # PCIe bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end + + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x15d9 0x2009 + chip superio/serverengines/pilot + device pnp 4e.0 on # unknown + io 0x60 = 0xf00 + end + + device pnp 4e.1 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 4e.3 on # unknown + io 0x60 = 0xe00 + io 0x62 = 0x200 + io 0x64 = 0x204 + io 0x66 = 0x208 + end + + device pnp 4e.4 off end # unknown + device pnp 4e.5 off end # unknown + device pnp 4e.6 off end # unknown + device pnp 4e.7 off end # unknown + device pnp 4e.8 on # IPMI + io 0x60 = 0xca4 + io 0x62 = 0xca5 + end + + device pnp 4e.9 on # IPMI + io 0x60 = 0xca2 + io 0x62 = 0xca3 + end + + device pnp 4e.a off end # unknown + + end + chip superio/smsc/smscsuperio + device pnp 2e.0 off end + device pnp 2e.3 on # LPT + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 off end + device pnp 2e.5 off end + + device pnp 2e.7 on # KBC + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + + end + device pnp 2e.a off end + end + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on + end # SMBUS + end + end +end diff --git a/src/mainboard/fsc/tx200s3/irq_tables.c b/src/mainboard/fsc/tx200s3/irq_tables.c new file mode 100644 index 0000000..84f456a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/irq_tables.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Thomas Jourdan thomas.jourdan@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x2670, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/fsc/tx200s3/mainboard.c b/src/mainboard/fsc/tx200s3/mainboard.c new file mode 100644 index 0000000..08d642a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/mainboard.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <delay.h> +#include <arch/coreboot_tables.h> +#include "chip.h" +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <smbios.h> +#include <string.h> +#include <../../../drivers/ipmi/ipmi_kcs.h> + +static const unsigned char ipmi_acpi_poweron[] = { 0xa0, 0x7f }; +static const unsigned char ipmi_boot_wdt_off[] = { 0x80, 0x28, 0x00, 0x0a, 0xc0 }; +static const unsigned char ipmi_clear_errors[] = { 0x80, 0x28, 0x00, 0x08, 0x01 }; + +static void mainboard_enable(device_t dev) +{ + unsigned char ipmi_response[32]; + int i, ret; + + ret = ipmi_kcs_message(0xca2, IPMI_NETFN_APPLICATION, 0, IPMI_CMD_ACPI_POWERON, + ipmi_acpi_poweron, sizeof(ipmi_acpi_poweron), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + + ret = ipmi_kcs_message(0xca2, 0x2e, 0, 0xf1, + ipmi_boot_wdt_off, sizeof(ipmi_boot_wdt_off), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + + ret = ipmi_kcs_message(0xca2, 0x2e, 0, 0xf1, + ipmi_clear_errors, sizeof(ipmi_clear_errors), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + +} + +static int smbios_data(device_t dev, int *handle, unsigned long *current) +{ + struct smbios_type38 *t = (struct smbios_type38 *)*current; + int len = sizeof(struct smbios_type38); + + memset(t, 0, sizeof(struct smbios_type38)); + t->type = 38; + t->handle = *handle++; + t->length = len; + t->interface_type = 1; /* KCS */ + t->ipmi_rev = 0x15; + t->i2c_slave_addr = 0x24; + t->nv_storage_addr = 0xff; + t->base_address = 0xca3; + t->base_address_modifier = 0; + *current += len; + return len - 1; /* FIXME: why? */ + +} + +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER) + .enable_dev = mainboard_enable, + .get_smbios_data = smbios_data, +}; + diff --git a/src/mainboard/fsc/tx200s3/mptable.c b/src/mainboard/fsc/tx200s3/mptable.c new file mode 100644 index 0000000..b95e6b9 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/mptable.c @@ -0,0 +1,68 @@ +/* generated by MPTable, version 2.0.15*/ +/* as modified by RGM for coreboot */ +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +#define INTA 0x00 +#define INTB 0x01 +#define INTC 0x02 +#define INTD 0x03 + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &isa_bus); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, 0x9, 0x20, IO_APIC_ADDR + 0x80000); + + /* Legacy Interrupts */ + mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x03 << 2) | INTA, 0x8, 0x10); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x08 << 2) | INTA, 0x8, 0x10); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1c << 2) | INTA, 0x8, 0x10); + + /* USB ports */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTA, 0x8, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTB, 0x8, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTC, 0x8, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTD, 0x8, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTA, 0x8, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (0x00 << 2) | INTA, 0x8, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | INTA, 0x8, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x02 << 2) | INTA, 0x8, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | INTA, 0x8, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x03 << 2) | INTA, 0x9, 0x3); + + /* MPT SAS */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, (0x05 << 2) | INTA, 0x8, 0x15); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/fsc/tx200s3/romstage.c b/src/mainboard/fsc/tx200s3/romstage.c new file mode 100644 index 0000000..343ef2a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/romstage.c @@ -0,0 +1,214 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <superio/serverengines/pilot/early_serial.c> +#include <northbridge/intel/i5000/raminit.h> +#include "northbridge/intel/i3100/i3100.h" +#include "southbridge/intel/i3100/i3100.h" +#include <southbridge/intel/i3100/early_smbus.c> +#include <delay.h> + +#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RCBA_RPC 0x0224 /* 32 bit */ +#define RCBA_HPTC 0x3404 /* 32 bit */ +#define RCBA_GCS 0x3410 /* 32 bit */ +#define RCBA_FD 0x3418 /* 32 bit */ + +static void early_config(void) +{ + u32 gcs, rpc, fd; + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); + + /* Disable watchdog */ + gcs = read32(DEFAULT_RCBA + RCBA_GCS); + gcs |= (1 << 5); /* No reset */ + write32(DEFAULT_RCBA + RCBA_GCS, gcs); + + /* Configure PCIe port B as 4x */ + rpc = read32(DEFAULT_RCBA + RCBA_RPC); + rpc |= (3 << 0); + write32(DEFAULT_RCBA + RCBA_RPC, rpc); + + /* Disable Modem, Audio, PCIe ports 2/3/4 */ + fd = read32(DEFAULT_RCBA + RCBA_FD); + fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); + write32(DEFAULT_RCBA + RCBA_FD, fd); + + /* Enable HPET */ + write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7)); + + /* Setup sata mode */ + pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40); +} + +#define DEFAULT_GPIOBASE 0x1180 +static void setup_gpio(void) +{ + pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4)); + + outl(0xff0cffe7, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xed00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0x53990000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x0000bfe7, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030300, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ +} + +static void i5000_lpc_config(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x360f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x10); + + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0xe01); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0xca1); +} + +int mainboard_set_fbd_clock(int speed) +{ + switch(speed) { + case 533: + smbus_write_byte(0x6f, 0x80, 0x21); + return 0; + case 667: + smbus_write_byte(0x6f, 0x80, 0x23); + return 0; + default: + printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed); + die(""); + return -1; + } +} + +void main(unsigned long bist) +{ + if (bist == 0) + enable_lapic(); + + i5000_lpc_config(); + + pilot_enable_serial(PNP_DEV(0x4e, 2), 0x3f8); + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + early_config(); + + setup_gpio(); + + enable_smbus(); + + /* setup PCIe MMCONF base address */ + pci_write_config32(PCI_DEV(0, 16, 0), 0x64, + CONFIG_MMCONF_BASE_ADDRESS >> 16); + + /* These are smbus write captured with serialice. They + seem to setup the clock generator */ + + smbus_write_byte(0x6f, 0x88, 0x1f); + smbus_write_byte(0x6f, 0x81, 0xff); + smbus_write_byte(0x6f, 0x82, 0xff); + smbus_write_byte(0x6f, 0x80, 0x23); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); + i5000_fbdimm_init(); + smbus_write_byte(0x69, 0x01, 0x01); + + device_t dev = PNP_DEV(0x4e, 0); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xf00); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 3); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xe00); + pnp_set_iobase(dev, 0x62, 0x200); + pnp_set_iobase(dev, 0x64, 0x204); + pnp_set_iobase(dev, 0x66, 0x208); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 4); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 5); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 6); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 7); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 8); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xca4); + pnp_set_iobase(dev, 0x62, 0xca5); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 9); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xca2); + pnp_set_iobase(dev, 0x62, 0xca3); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 0x0a); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); +}