coreboot-3.0.974 Fri Oct 31 15:11:04 PDT 2008 starting... (console_loglevel=8) Choosing fallback boot. LAR: Attempting to open 'fallback/initram/segment0'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 1008 LAR: seen member normal/initram/segment0@0xfffc0440, size 8876 LAR: seen member normal/stage2/segment0@0xfffc2740, size 1 LAR: seen member normal/stage2/segment1@0xfffc27a0, size 17676 LAR: seen member normal/stage2/segment2@0xfffc6d00, size 579 LAR: seen member bootblock@0xffffafc0, size 20480 LAR: File not found! LAR: Run file fallback/initram/segment0 failed: No such file. Fallback failed. Try normal boot LAR: Attempting to open 'normal/initram/segment0'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 1008 LAR: seen member normal/initram/segment0@0xfffc0440, size 8876 LAR: CHECK normal/initram/segment0 @ 0xfffc0440 start 0xfffc0490 len 8876 reallen 8876 compression 0 entry 0x00001475 loadaddre0 Entry point is 0xfffc1905 In initram.c main() Enabling Via V-Link pci_conf1_find_on_bus: bus 0, find 0x1106:3227 pci_conf1_find_on_bus: bus 1, find 0x1106:3227 pci_conf1_find_on_bus: bus 0, find 0x1106:0571 pci_conf1_find_on_bus: bus 1, find 0x1106:0571 Enabling shadow ram pci_conf1_find_on_bus: bus 0, find 0x1106:3227 pci_conf1_find_on_bus: bus 1, find 0x1106:3227 VT8237R Power management controller found at 0x8800 SMBus Ready/Completed Successfully Configuring DRAM Bank 0 SMBus Read from DIMM 80 at address 0x1f SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x80 SMBus Ready/Completed Successfully Found 512MB module in slot 0 Setting Top of Usable DRAM to 512MB Calculating tWR and tRFC SMBus Read from DIMM 80 at address 0x24 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x3c SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x2a SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x69 SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x28 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x0 SMBus Ready/Completed Successfully Calculating tRAS and CAS SMBus Read from DIMM 80 at address 0x1e SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x27 SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x12 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x38 SMBus Ready/Completed Successfully Calculating tRRD, tRTP, and tWTR SMBus Read from DIMM 80 at address 0x1c SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x1e SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x26 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x1e SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x25 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x1e SMBus Ready/Completed Successfully Calculating tRCD and tRP SMBus Read from DIMM 80 at address 0x1d SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x3c SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x1b SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x3c SMBus Ready/Completed Successfully calculating MA map SMBus Read from DIMM 80 at address 0x5 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x60 SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x4 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0xa SMBus Ready/Completed Successfully Setting Memory Address Map type to 0x1 Configuring DRAM Bank 1 SMBus Read from DIMM 0 at address 0x1f SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready Device error Read: 0x0 SMBus Ready/Completed Successfully No memory in slot 1 RAM Enable 1: Apply NOP Sending RAM command 'No-op' to 0x0 RAM Enable 2: Precharge all Sending RAM command 'Precharge' to 0x0 RAM Enable 3: Mode register set (DLL Reset) Sending RAM command 'MRS' to 0x12000 RAM Enable 4: Precharge all Sending RAM command 'Precharge' to 0x0 RAM Enable 5: CBR Sending RAM command 'CBR' to 0x0 RAM Enable 6: Mode register set (OCD Calibration) Mode Register Set (MRS) value is 0x1001d8 Sending RAM command 'MRS' to 0x1001d8 RAM Enable 7: Normal operation Sending RAM command 'Normal' to 0x0 Sending RAM command 'Normal' to 0x30 run_file returns with 0 Done RAM init code In hardware_stage1()
resets at this point and restarts. Very slow, as though it were not caching ROM?
ron