Hi Rafael,
On 14.01.20 02:18, Rafael Send wrote:
*2)* Modify fmap - currently looks like this:
... and it should become:
FLASH@0xff800000 0x1000000 { <- new chip size
you should also lower the offset to 0xff000000. The flash is (assumed) to be mapped right below 4GiB. So it should end (sum of the two numbers) at 0x100000000 (excluding).
Question: I read that an FMAP file overrides CBFS_SIZE, if such is provided.Since the coreboot .config still says CBFS_SIZE=0x200000, but an FMAP has always been provided, is it true that 0x200000 was never the result / used?
That's correct.
Am I missing any steps, and are the above modifications correct?
What happened to 3)? :)
Don't you need an ME image? how does it get to the new flash chip?
You also have to increase the size of the BIOS region in the IFD.
The IFD also contains a small table about flash chips (e.g. to know the erase opcode / block size). I'm not sure if you need to adapt it or if the PCH would fall back to automatic discovery via SFDP. Might also depend on the PCH generation. I would match it with the new chip to be on the safe side.
IMHO, the worst thing you can do is to assume that it will work on the first try. Better be prepared for more external flashing.
Nico