I am told by those who have sources that commercial bios'es are an large mess of assembly code with lots of repeated code and fixes for hardware that has not existed for 10 years. I find these stories believable ...
Actually that brings up a few questions I had about the 430TX chipset support in LinuxBIOS... The DRAM initialization seems to be utterly mangled, with Eric's code winning out (since it seems to work. :-) -- but I have seen a few register initializations which I haven't been able to find in my 430TX documentation.
Things like register 0x90 (in raminit.inc it's called "Error Control Register") and using eight read cycles to reset either the memory or the controller, I'm not sure... Does anyone have any recollection of where this type of information was found? If I do a (fairly large) cleanup of the 430TX ram init code, would it be accepted into CVS or is it how it is for specific reasons?
BTW: I found out why LinuxBIOS kept resetting -- the FDC37N958FR's internal 8051 core has a watchdog which is initialized to about 4s on POR... I was playing with the ramtest.inc and delays in the mem init of the northbridge and got nearer or farther in the boot.