Hi Nico,
Most notable is that for the failing memory configurations the '[DEBUG] Stored timings CRC16 mismatch.' message is returned, after which `[DEBUG] SPD probe channel0, slot1` is triggered, which seems to fail: `ERROR: SPD CRC failed!!!`
Had a quick look at the code that prints this error message (src/device/dram/ddr3.c) and this is very likely due to bad SPD data/checksum on the DIMM on channel 0, slot 1. The SPD EEPROM has a checksum and that checksum doesn't seem match with the calculated one. So this probably isn't a problem with the board or the coreboot port for it.
I assume that there was no previous successful boot with the given RAM configuration, so the "Stored timings CRC16 mismatch" likely isn't the problem, but just means that the MRC cache contents are outdated and that the full SPD EEPROM contents have to be read from the DIMMs and a full DRAM training has to be done in this case.
I'm a bit surprised that only some of the DIMMs work despite them all being of the same type. Maybe try dumping and comparing the SPD EEPROM contents; maybe it's corrupted on one of the DIMMs. When the DIMMs are all identical, taking a good SPD image from one and flashing it to the corrupted one might be worth a try; make sure that the DIMMs are exactly the same before trying this though and always have backups of the previous contents.
Regards, Felix