Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/875
-gerrit
commit d9462c6dca942bed9a609cc40572912bb33f0558 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Fri Apr 6 04:03:50 2012 +0300
Fix support for RAM-less multi-processor init
Fix regression after commit: 7dfe32c5408916b6cb23f1ec48e473e1c728d300
Only align 16-bit entry on platforms that really require it, indicated by selecting SIPI_VECTOR_IN_ROM in CPU Kconfig. Disable assertion test of AP_SIPI_VECTOR for platforms not depending on this feature.
Build of romstage should be fixed to get the vector address from bootblock build automatically.
Change-Id: Ide470833c0254df1a9ff708369ab1c095ccfb98d Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/arch/x86/Kconfig | 7 +++++++ src/arch/x86/init/ldscript_failover.lb | 14 +++++++++----- src/cpu/intel/socket_mPGA604/Kconfig | 1 + 3 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index f49d09b..6d56ec6 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -8,6 +8,13 @@ config AP_IN_SIPI_WAIT default n depends on ARCH_X86
+# Aligns 16bit entry code in bootblock so that hyper-threading CPUs +# can boot AP CPUs to enable their shared caches. +config SIPI_VECTOR_IN_ROM + bool + default n + depends on ARCH_X86 + config RAMBASE hex default 0x100000 diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 61c3d2a..d6940ee 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -30,10 +30,11 @@ TARGET(binary) SECTIONS { /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs - * with Startup IPI message without RAM. + * with Startup IPI message without RAM. Align .rom to next 4 byte + * boundary anyway, so no pad byte appears between _rom and _start. */ .bogus ROMLOC_MIN : { - . = ALIGN(4096); + . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); ROMLOC = .; } >rom = 0xff
@@ -52,11 +53,14 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - + (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
/* Post-check proper SIPI vector. */ - _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment"); - _bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR"); + _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0), + "Bad SIPI vector alignment"); + _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), + "Address mismatch on AP_SIPI_VECTOR");
/DISCARD/ : { *(.comment) diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 4fa7569..0d4d45f 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -11,6 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select MMX select SSE select UDELAY_TSC + select SIPI_VECTOR_IN_ROM
# mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on