Konstantin,
I note that you have experience of the CN400. I am currently trying to develop C3/CN400 support (Actually Luke CoreFusion) support, but I am having diffculty with the early RAM init.
I've been looking at the VX800 code for comparison.
Other than the fact that the VX800 code is mostly written for DDR2 can you tell me if the general ram init sequence for the CN400 should be the same. From the bits that are being tweaked in the Vx800 code, it looks like the CN400 DLL/NB reset sequence should be similar after setting the DRAM frequency.
I'd appreciate any help you could offer in outlining any key sequence steps in the RAM init for the CN400.
Thanks, Jon
-----Original Message-----
Konsstantin Lazarev wrote:
Hello,
I am interested to participate in development of coreboot support for VIA VX8xx+Nano. I have experience in adaptation of LinuxBIOS for
GeodeLX
platforms in a past. And I have experience in low-level programming
and
vendor BIOSes (GS, Phoenix) adaptation for other VIA chipsets (CN400, VT8237, CX700, C3, C7). Now I am working on bringing up VX800+Nano based platform (hardware is available) and very interested in moving
it
to open-source BIOS instead of vendor one. And any existing coreboot source code for VIA VX8xx would be very helpful. I will be glad to contribute my work to open-source BIOS project. I (my employer) have
NDA
signed with VIA.
Thank you, Konstantin Lazarev.
SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ********************************************************************