After some reading on the PCI spec I am sure that enumerating of the PCI devices on my epia board is not working as it should be.
I assume everyone here is using a recent version of the code. As no one other than those of us using the epia board are having problems, I must assume it is a problem with the VIA chipset and not a bug in Linuxbios.
Booting using a current version, I get the following when enumerating the PCI devices (reading resources)
PCI: 00:11.1 20 * [0x00000c00 - 0x00000c0f] io PCI: 00:11.1 10 * [0x00000c10 - 0x00000c17] io PCI: 00:11.1 18 * [0x00000c20 - 0x00000c27] io PCI: 00:11.1 14 * [0x00000c30 - 0x00000c33] io PCI: 00:11.1 1c * [0x00000c40 - 0x00000c43] io
From a working system using lspci I have the following
00:11.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: VIA Technologies, Inc. Unknown device 6010 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Region 4: I/O ports at d000 [size=16] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 06 11 71 05 07 00 90 02 06 8a 01 01 00 20 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 d0 00 00 00 00 00 00 00 00 00 00 06 11 10 60
10h - 1Ch above are all 0, so I assume that there are no BASE ADDRESS registers allocated here. One thing I am curious about is that according to the PCI spec (I only have version 2.1) the base address registers start at 10h, so why, in the above , does the IDE controller, and in fact most of the devices on the board use the higher base address registers ?
Another question I have is the fact that 20h contians d001h. The PCI spec does mention that a device may have don't care bits in the base address. So can I assume that, that is the case here ?
Or is there some strange bit shifting going on ?
What confuses me is that on an earlier version (head version 2401) this worked. Comparing the two versions I can see there have been changes to the PCI parts of the code, but nothing to dramatic, and as I have said no one else seems to be having problems.
The EPIA code is more or less the same, just a few text changes in the debug so was it just working by luck before ?
Does anyone have any thoughts on why the enumeration is wrong ?
I guess I am looking at a wrongly configured southbridge chip or northbridge chip.
Ben.