Myles Watson wrote:
So each AP has some part of RAM to copy the buffer to?
the way SMP works, the BSP sets up its ram. At that point, the APs can use the BSP ram.
For Opterons where each node has its own RAM this is a little bit more complex, right?
No, not really. This is already the complex case. Many systems only have one memory controller. But on all coreboot systems, even those with multiple memory controllers, the controllers are all set up by the BSP. Parallelizing here makes only very little sense.
The reason we're parallelizing is you have to clear memory if you have ECC on some (older?) systems where the memory controller is incapable of doing that automatically. So when we have to clear 32G at a rate of 3 or 6GB/s we want to put that load on several CPUs, so it's 1-2s instead of 5-10. But the ram is all there at this point, and can be transparently accessed by all CPUs.
Stefan