I have the same module DRAM as more people that have written in the list that not work with the initialization, and have tested the code of Corey (1000 thanks Corey), and have the same results, but have found a aproximation to the solution:
This DDR2 module works with Corey memory initialization with a little change with another values that another mainboard finds with the same DDR2 module, and then works, with the C7/CN700 but y not known what are the bits that differ with the Corey version.
The changes for /src/northbridge/via/cn700/raminit.c (marked with a //by another mainboard) ......chunk of sdram_enable()...... /* (E)MRS values are from the BPG. No direct explanation is given, but * they should somehow conform to the JEDEC DDR2 SDRAM Specification * (JESD79-2C). */ // do_ram_command( RAM_COMMAND_MRS, 0x0022d8);//by Corey do_ram_command( RAM_COMMAND_MRS, 0x101258);//by another mainboard // do_ram_command( RAM_COMMAND_MRS, 0x2258);//a second mainboard
// 7. Mode register set. PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); // do_ram_command( RAM_COMMAND_MRS, 0x21c20);//default OCD calibration by do_ram_command( RAM_COMMAND_MRS, 0x121c20);//By another mainboard // do_ram_command( RAM_COMMAND_MRS, 0x20020);//exit calibration mode do_ram_command( RAM_COMMAND_MRS, 0x120020);//by another mainboard
// 8. Normal operation PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n"); do_ram_command( RAM_COMMAND_NORMAL, 0); ......chunk of sdram_enable()......
Only have a problem with these values. The RAM works correctly all 511MB, i can write memory and then test it... but when i jumps to a program loaded in memory, hangs with the first Branch instruction, for example "je". I not wise, if the C7/CN700 can have a optimization system with branches, that requires a feature with SDRAM activated. If the code loaded not have branches, it works. Is for me absurd....
El vie, 21-12-2007 a las 02:44 +0100, linuxbios-request@linuxbios.org escribió:
KVR533D2N4/512,