This patch fixes ht chain handling.
include/device/path.h: Add a ht_path type to hold chain number and UnitID.
include/device/hypertransport.h: Remove offset_unitid from prototype.
mainboard/amd/serengeti/dts: Update to use ht@chain,unitid. Add 8132 devices. Add pci_X for devices that would otherwise collide. Since setting the UnitID for an HT device affects the devfn of all the PCI devices on the chip, they all start at 0,0 and go from there. If you look in a data sheet it will say Dev A, function 2 and Dev B, function 3 etc. These become pci@0,2 and pci@ 1,3.
device/hypertransport.c: Remove many #if statements and rely on the dts. The idea here is that we change HT devices to PCI at enumeration. That makes it so that they can be scanned on the normal PCI bus. The code is set up so that it can also scan without being given ht UnitIDs ht@chain, and then it assigns them in the order it finds them.
device/pci_device.c: Add an error if there's a broken BAR. Remove an overly verbose statement Not setting VID... Add the path to a debug statement about leftover devices.
device/device_util.c: Add HT support in dev_path().
device/pci_ops.c Make the debug statement more clear when there's a loop.
northbridge/amd/k8/pci.c: Remove offset_unitid
util/dtc/flattree.c: Add support for ht@chain,unitid. Remove broken link code. This code generated a new link when there was a sibling of a bridge that was also a bridge. This breaks Serengeti because it has two siblings that are bridges, but they are not on separate links.
Signed-off-by: Myles Watson mylesgw@gmail.com
Here's the resulting device tree:
Notice that the only dynamic (discovered) devices are the plug-in cards.
Show all devs in tree form...After phase 3. root(Root Device): enabled 1 have_resources 0 cpus(CPU: 00): enabled 1 have_resources 0 apic_0(APIC: 00): enabled 1 have_resources 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 domain_0_pci_18_0(PCI: 00:18.0): enabled 1 have_resources 0 domain_0_pci_18_0_ht_0_6(PCI: 00:06.0): enabled 1 have_resources 0 domain_0_pci_18_0_ht_0_6_pci_0_0(PCI: 01:00.0): enabled 1 have_resources 0 domain_0_pci_18_0_ht_0_6_pci_0_1(PCI: 01:00.1): enabled 1 have_resources 0 domain_0_pci_18_0_ht_0_6_pci_0_2(PCI: 01:00.2): enabled 0 have_resources 0 domain_0_pci_18_0_ht_0_6_pci_1_0(PCI: 01:01.0): enabled 0 have_resources 0 dynamic PCI: 01:04.0(PCI: 01:04.0): enabled 1 have_resources 0 dynamic PCI: 01:05.0(PCI: 01:05.0): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_0(PCI: 00:07.0): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e(IOPORT: 2e): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_0(PNP: 002e.0): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_1(PNP: 002e.1): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_2(PNP: 002e.2): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_3(PNP: 002e.3): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_5(PNP: 002e.5): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_6(PNP: 002e.6): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_7(PNP: 002e.7): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_8(PNP: 002e.8): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_9(PNP: 002e.9): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_10(PNP: 002e.a): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_11(PNP: 002e.b): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_1(PCI: 00:07.1): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_2(PCI: 00:07.2): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_3(PCI: 00:07.3): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_5(PCI: 00:07.5): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_6(PCI: 00:07.6): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_7(PCI: 00:07.7): enabled 1 have_resources 0 domain_0_pci_18_0_ht_0_a(PCI: 00:0a.0): enabled 1 have_resources 0 domain_0_pci_18_0_pci_a_0_1(PCI: 00:0a.1): enabled 1 have_resources 0 domain_0_pci_18_0_pci_a_1_0(PCI: 00:0b.0): enabled 1 have_resources 0 domain_0_pci_18_0_pci_a_1_1(PCI: 00:0b.1): enabled 1 have_resources 0 domain_0_pci_18_1(PCI: 00:18.1): enabled 1 have_resources 0 domain_0_pci_18_2(PCI: 00:18.2): enabled 1 have_resources 0 domain_0_pci_18_3(PCI: 00:18.3): enabled 1 have_resources 0
I'm hoping that this gets us to the point where we can work on getting video working.
Here are some of the next steps: - Get video working. - Remove #ifs from k8 chain code. - Add the rest of the devices to the dts (other processors and AGP bridge.) - Unify SIO code. - Remove links structure? - K8 doesn't need them, does anyone?
Thanks, Myles