Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1688
-gerrit
commit 543d38dd63b49a92f8be113b85f4d065fa290978 Author: Sameer Nanda snanda@chromium.org Date: Wed Jul 25 16:11:40 2012 -0700
Leave power control registers unlocked
To allow easy experimentation with thermals, leave power control registers unlocked.
Change-Id: Ia53065f3f220c2faed58e7d53e60c3f169ae58ec Signed-off-by: Sameer Nanda snanda@chromium.org --- src/cpu/intel/model_206ax/finalize.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 68cef8d..4ed5d1e 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -49,11 +49,24 @@ void intel_model_206ax_finalize_smm(void) if (cpuid_ecx(1) & (1 << 25)) msr_set_bit(MSR_FEATURE_CONFIG, 0);
+#ifdef LOCK_POWER_CONTROL_REGISTERS + /* + * Lock the power control registers. + * + * These registers can be left unlocked if modifying power + * limits from the OS is desirable. Modifying power limits + * from the OS can be especially useful for experimentation + * during early phases of system bringup while the thermal + * power envelope is being proven. + */ + msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); msr_set_bit(MSR_PKG_POWER_LIMIT, 63); msr_set_bit(MSR_PP0_POWER_LIMIT, 31); msr_set_bit(MSR_PP1_POWER_LIMIT, 31); +#endif + msr_set_bit(MSR_MISC_PWR_MGMT, 22); msr_set_bit(MSR_LT_LOCK_MEMORY, 0); }