On Mon, Apr 07, 2008 at 03:06:29PM -0600, Marc Jones wrote:
Bring Fam10 memory controller init up to date with the latest AMD BKDG recomendations.
Changes include the following: fix > 4GB dqs tests fix channel interleaving fix memory hoisting across nodes ecc memory scrub updates debug print changes minor cleanups
Signed-off-by: Marc Jones (marc.jones@amd.com)
NAK.
Index: coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c
--- coreboot-v2.orig/src/northbridge/amd/amdmct/mct/mct_d.c 2008-04-07 11:28:02.000000000 -0600 +++ coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c 2008-04-07 14:45:52.000000000 -0600 @@ -1,7 +1,7 @@ /*
- This file is part of the coreboot project.
- Copyright (C) 2007 Advanced Micro Devices, Inc.
- Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
@@ -277,12 +277,15 @@ mctHookAfterCPU(); /* Setup external northbridge(s) */
print_t("mctAutoInitMCT_D: DQSTiming_D\n");
- DQSTiming_D(pMCTstat, pDCTstatA); /* Get Receiver Enable and DQS signal timing*/
- DQSTiming_D(pMCTstat, pDCTstatA); /* Get Receiver Enable and DQS signal timing */
- print_t("mctAutoInitMCT_D: UMAMemTyping_D\n");
- UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */
Please keep code changes and whitespace changes apart. In particular when changing things like these (that are not very well known) I think that is important.
print_t("mctAutoInitMCT_D: :OtherTiming\n"); mct_OtherTiming(pMCTstat, pDCTstatA);
- if (ReconfigureDIMMspare_D(pMCTstat, pDCTstatA)) { /* RESET# if 1st pass of DIMM spare enabled*/
- if (ReconfigureDIMMspare_D(pMCTstat, pDCTstatA)) { /* RESET# if 1st pass of DIMM spare enabled */
..it goes on..
goto restartinit;
}
@@ -290,7 +293,7 @@ InterleaveChannels_D(pMCTstat, pDCTstatA);
print_t("mctAutoInitMCT_D: ECCInit_D\n");
- if (ECCInit_D(pMCTstat, pDCTstatA)) { /* Setup ECC control and ECC check-bits*/
- if (ECCInit_D(pMCTstat, pDCTstatA)) { /* Setup ECC control and ECC check-bits */
..and on.
//Peter