Author: uwe Date: Mon Dec 6 19:17:01 2010 New Revision: 6143 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6143
Log: Winbond W83627HF: Use existing functions instead of open-coding.
Use w83627hf_set_clksel_48() where needed instead or open-coding the same functionality, and also use w83627hf_enable_serial() instead of w83627hf_enable_dev() (which does exactly the same, but isn't wrapped in the enter/exit config mode functions).
Abuild-tested.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/src/mainboard/msi/ms6178/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/epia-n/romstage.c
Modified: trunk/src/mainboard/msi/ms6178/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6178/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/msi/ms6178/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -33,18 +33,15 @@ #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0)
void enable_smbus(void); int smbus_read_byte(u8 device, u8 address);
void main(unsigned long bist) { - /* FIXME */ - outb(0x87, 0x2e); - outb(0x87, 0x2e); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); + w83627hf_set_clksel_48(DUMMY_DEV); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - outb(0x87, 0xaa);
uart_init(); console_init();
Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -48,6 +48,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
@@ -193,10 +194,8 @@ if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init(); console_init();
Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -51,6 +51,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0)
static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -122,10 +123,8 @@ if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init(); console_init();
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -50,6 +50,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -125,10 +126,8 @@
post_code(0x32);
- pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init(); console_init();
Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -50,6 +50,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0)
static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -176,10 +177,8 @@
post_code(0x32);
- pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init(); console_init();
Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -16,13 +16,14 @@ #include "debug.c" #include "watchdog.c" #include "reset.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0)
#define DEVPRES_CONFIG ( \ DEVPRES_D1F0 | \ @@ -63,11 +64,8 @@ skip_romstage(); }
- /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init();
Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -17,13 +17,14 @@ #include "watchdog.c" #include "reset.c" #include "x6dhe_g_fixups.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0)
#define DEVPRES_CONFIG ( \ DEVPRES_D1F0 | \ @@ -60,11 +61,8 @@ skip_romstage(); }
- /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init();
Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -15,13 +15,14 @@ #include "watchdog.c" #include "reset.c" #include "x6dhr_fixups.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0)
#define DEVPRES_CONFIG ( \ DEVPRES_D0F0 | \ @@ -59,11 +60,8 @@ skip_romstage(); }
- /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init();
Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -15,13 +15,14 @@ #include "watchdog.c" #include "reset.c" #include "x6dhr2_fixups.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0)
#define DEVPRES_CONFIG ( \ DEVPRES_D0F0 | \ @@ -59,11 +60,8 @@ skip_romstage(); }
- /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init();
Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/via/epia-m700/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -46,6 +46,7 @@ #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0)
/* * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: @@ -384,7 +385,7 @@ */ pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); /* EmbedComInit(); */ - w83697hf_set_clksel_48(SERIAL_DEV); + w83697hf_set_clksel_48(DUMMY_DEV); w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); /* enable_vx800_serial(); */
Modified: trunk/src/mainboard/via/epia-n/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-n/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/via/epia-n/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -38,6 +38,7 @@ #include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0)
static const struct mem_controller ctrl = { .d0f0 = 0x0000, @@ -109,7 +110,7 @@ /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
- w83697hf_set_clksel_48(SERIAL_DEV); + w83697hf_set_clksel_48(DUMMY_DEV); w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init();