On Fri, Jun 09, 2017 at 12:47:59PM +0800, 王翔 wrote:
On Friday,June 9, 2017 at 12:34 PM,王翔 wrote:
[...]
I get source frome https://github.com/riscv/riscv-tools.git. Compare the difference with https://github.com/riscv/riscv-isa-sim/pull/53 and fix the code. The difference of Our patch is **UART_BASE**. You use 0x02100000, me use 0x40001000. In my test 0x40001000 can be work with **coreboot**, but 0x02100000 can not. My patch is in the attachment of the message.
I'm sorry. I not change **uintptr_t uart_platform_base(int idx)**
I've updated https://github.com/riscv/riscv-isa-sim/pull/53 and uploaded a coreboot patch to use the new UART address¹:
https://review.coreboot.org/#/c/20126/
What did you test? How did it fail?
I test by **spike**. I have report the patch. https://review.coreboot.org/#/c/20043/ https://review.coreboot.org/#/c/20105/
But these bugs still exist.
Thank you for these patches.
Regards, Jonathan Neuschäfer
¹) It wasn't strictly necessary to change the UART address, but I think 0x02100000 fits better into the current address map. The old patch is available at https://github.com/neuschaefer/riscv-isa-sim/commits/uart-old-v1.