[coreboot] [PATCH] AMD F14 persimmon and e350m1: use standard pci config functions

[Scott Duplichan]

AMD F14 persimmon and e350m1: replace inline cf8/cfc pci config
access with pci_read_config and pci_write_config function calls.

Signed-off-by: Scott Duplichan

Index: src/mainboard/amd/persimmon/romstage.c
===================================================================
--- src/mainboard/amd/persimmon/romstage.c	(revision 6637)
+++ src/mainboard/amd/persimmon/romstage.c	(working copy)
@@ -73,21 +73,20 @@
   // early enable of PrefetchEnSPIFromHost
   if (boot_cpu())
     {
-    __outdword (0xcf8, 0x8000a3b8);
-    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
+    device_t dev = PCI_DEV(0, 0x14, 3);
+    pci_write_config8(dev, 0xbb, pci_read_config8(dev, 0xbb) | 1);
     }

// early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {
     volatile u32 *spiBase = (void *) 0xa0000000;
-    u32 save;
-    __outdword (0xcf8, 0x8000a3a0);
-    save = __indword (0xcfc);
-    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
+    device_t dev = PCI_DEV(0, 0x14, 3);
+    u32 save = pci_read_config32(dev, 0xa0);
+    pci_write_config32(dev, 0xa0, (u32)spiBase | 2); // set temp MMIO base
     spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
     spiBase [0] |= 1 << 18; // fast read enable
-    __outdword (0xcfc, save); // clear temp base
+    pci_write_config32(dev, 0xa0, save);
     }

if (!cpu_init_detectedx && boot_cpu()) {
Index: src/mainboard/asrock/e350m1/romstage.c
===================================================================
--- src/mainboard/asrock/e350m1/romstage.c	(revision 6637)
+++ src/mainboard/asrock/e350m1/romstage.c	(working copy)
@@ -58,21 +58,20 @@
   // early enable of PrefetchEnSPIFromHost
   if (boot_cpu())
     {
-    __outdword (0xcf8, 0x8000a3b8);
-    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
+    device_t dev = PCI_DEV(0, 0x14, 3);
+    pci_write_config8(dev, 0xbb, pci_read_config8(dev, 0xbb) | 1);
     }

// early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {
     volatile u32 *spiBase = (void *) 0xa0000000;
-    u32 save;
-    __outdword (0xcf8, 0x8000a3a0);
-    save = __indword (0xcfc);
-    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
+    device_t dev = PCI_DEV(0, 0x14, 3);
+    u32 save = pci_read_config32(dev, 0xa0);
+    pci_write_config32(dev, 0xa0, (u32)spiBase | 2); // set temp MMIO base
     spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
     spiBase [0] |= 1 << 18; // fast read enable
-    __outdword (0xcfc, save); // clear temp base
+    pci_write_config32(dev, 0xa0, save);
     }

if (!cpu_init_detectedx && boot_cpu()) {