I picked up the values programmed to the IDE controller. At the first part (*1) it scans the base address registers and finally assigns the PCI I/O (*2), at this point this is no longer legacy compatible. And *3 is setting it to native mode.
In the vt8231.c, there is confusion about conf->enable_native_ide variable. As the name suggests, it should DISABLE legacy mode if this variable is 1. But for reg 0x42 it does the opposite.
I don't know how this thing works, but in mainboard/via/epia/Config.lb, it's set to 1. register "enable_native_ide" = "1"
Also I've noticed in V1, base address registers are explicitly cleared to zero in southbridge_fixup. I don't see this code moved to V2. Perhaps we should have a better way to do this..
$ grep 0x89 /tmp/epialog | grep '^Write' Write config 32 bus 0, devfn 0x89, reg 0x10, val 0xffffffff *1 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0x1f1 Write config 32 bus 0, devfn 0x89, reg 0x14, val 0xffffffff Write config 32 bus 0, devfn 0x89, reg 0x14, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x14, val 0x3f5 Write config 32 bus 0, devfn 0x89, reg 0x18, val 0xffffffff Write config 32 bus 0, devfn 0x89, reg 0x18, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x18, val 0x171 Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0xffffffff Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0x375 Write config 32 bus 0, devfn 0x89, reg 0x20, val 0xffffffff Write config 32 bus 0, devfn 0x89, reg 0x20, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x20, val 0xcc01 Write config 32 bus 0, devfn 0x89, reg 0x24, val 0xffffffff Write config 32 bus 0, devfn 0x89, reg 0x24, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x24, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0x1c51 *2 Write config 32 bus 0, devfn 0x89, reg 0x14, val 0x1c71 Write config 32 bus 0, devfn 0x89, reg 0x18, val 0x1c61 Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0x1c81 Write config 32 bus 0, devfn 0x89, reg 0x20, val 0x1c41 Write config 8 bus 0, devfn 0x89, reg 0xd, val 0x40 Write config 8 bus 0, devfn 0x89, reg 0xc, val 0x10 Write config 16 bus 0, devfn 0x89, reg 0x4, val 0x81 Write config 8 bus 0, devfn 0x89, reg 0x42, val 0x9 Write config 8 bus 0, devfn 0x89, reg 0x40, val 0xb Write config 8 bus 0, devfn 0x89, reg 0x41, val 0xf2 Write config 8 bus 0, devfn 0x89, reg 0x43, val 0x35 Write config 8 bus 0, devfn 0x89, reg 0x44, val 0x18 Write config 8 bus 0, devfn 0x89, reg 0x45, val 0x1c Write config 8 bus 0, devfn 0x89, reg 0x9, val 0x8f *3 Write config 8 bus 0, devfn 0x89, reg 0x4, val 0x7 Write config 8 bus 0, devfn 0x89, reg 0x3c, val 0xb Write config 8 bus 0, devfn 0x89, reg 0x3c, val 0xb