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Kerry She (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/135
-gerrit
commit 5cb524a357dc0c3b4f959ca44a50b00c1dd76b77 Author: Kerry She <shekairui at gmail.com> Date: Thu Aug 18 18:03:44 2011 +0800
AMD F14 southbridge update
This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein.
Does this patch really have anything to do with "rec C0" CPUs ? It's all (welcome) southbridge code improvements as far as I can see.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans <frank.vibrans at amd.com> Signed-off-by: efdesign98 <efdesign98 at gmail.com> Signed-off-by: Kerry She <kerry.she at amd.com> Signed-off-by: Kerry She <shekairui at gmail.com>
In my opinion it would be unwise for this patch to go into the repository as a single commit. I would strongly prefer smaller patches with individual commit messages. Are you using git internally by the way ?
Below I give a rough outline of how one might break down this patch into THIRTY smaller ones. The line numbers might not be right due to multiple counting.
First a few comments:
Is "platform_cfg.h" the right name for a file containing mainboard-specific SB configs ? And are you expecting more than just southbridge configs to be in that file ?
There is still the issue of configs which missing from cfg.h/cfg.c/platform_cfg.h and which are thus undefined and dangerous.
sb800/late.c is looking much better than the earlier patch. You need to set the SATA pci device id according to the SATA controller mode, with something like this:
#if (SATA_MODE == NATIVE_IDE_MODE || SATA_MODE == LEGACY_IDE_MODE) .device = PCI_DEVICE_ID_ATI_SB800_SATA, //SATA IDE Mode (0x4390) #endif #if (SATA_MODE == AHCI_MODE || SATA_MODE == IDE_TO_AHCI_MODE) .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, //SATA AHCI Mode (0x4391) #endif ...etc... See southbridge/amd/cimx/sb900/late.c and vendorcode/amd/cimx/sb800/SB800.h for the rest.
Please do s/breif/brief/ on your patch.
There are still (outside your patch) some instances of "CINFIG".
======= Patch breakdown ======= ===============================
sb800: Remove CONFIG_AMD_CIMX_SB800 duplicate
Use CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 instead of CONFIG_AMD_CIMX_SB800
src/southbridge/amd/Makefile.inc | 4 +- src/southbridge/amd/cimx/sb800/Makefile.inc | 2 +- src/mainboard/advansus/a785e-i/Kconfig | 4 - src/mainboard/amd/inagua/Kconfig | 4 - src/mainboard/amd/persimmon/Kconfig | 4 - src/mainboard/asrock/e350m1/Kconfig | 4 -
sb900: Remove CONFIG_AMD_CIMX_SB900 duplicate
Use CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 instead of CONFIG_AMD_CIMX_SB900
src/mainboard/amd/torpedo/Kconfig | 4 - src/southbridge/amd/Makefile.inc | 4 +- src/southbridge/amd/cimx/sb900/Makefile.inc | 6 +-
sb800: Use common defines and routines instead of per board ones
Use platform defines and io routines instead of board-local routines in pmio.h /pmio.c.
src/mainboard/amd/persimmon/Makefile.inc | 1 - src/mainboard/advansus/a785e-i/Makefile.inc | 2 - src/mainboard/asrock/e350m1/Makefile.inc | 1 - src/mainboard/amd/inagua/Makefile.inc | 3 +- src/mainboard/advansus/a785e-i/mainboard.c | 24 +- src/mainboard/advansus/a785e-i/fadt.c | 81 +- src/mainboard/amd/inagua/fadt.c | 83 +- src/mainboard/amd/persimmon/fadt.c | 83 +- src/mainboard/asrock/e350m1/fadt.c | 83 +-
sb800: Use ReadPMIO in mainboards mptable code
src/mainboard/advansus/a785e-i/mptable.c | 10 +- src/mainboard/amd/persimmon/mptable.c | 8 +- src/mainboard/amd/inagua/mptable.c | 8 +- src/mainboard/asrock/e350m1/mptable.c | 8 +-
sb800: Remove mainboards' unused pmio code
src/mainboard/advansus/a785e-i/pmio.c | 53 - src/mainboard/advansus/a785e-i/pmio.h | 33 - src/mainboard/amd/persimmon/pmio.c | 55 - src/mainboard/amd/persimmon/pmio.h | 34 - src/mainboard/amd/inagua/pmio.c | 55 - src/mainboard/amd/inagua/pmio.h | 34 - src/mainboard/asrock/e350m1/pmio.c | 55 - src/mainboard/asrock/e350m1/pmio.h | 34 -
sb800: Move sb800_clk_output_48Mhz from a785e-i to sb800/early.c
src/mainboard/advansus/a785e-i/romstage.c | 19 +- src/southbridge/amd/cimx/sb800/early.c | 22 +-
sb800: Rename sb_poweron_init as sb_Poweron_Init
src/southbridge/amd/cimx/sb800/early.c | 22 +- src/mainboard/advansus/a785e-i/romstage.c | 19 +- src/mainboard/amd/inagua/romstage.c | 4 +- src/mainboard/amd/persimmon/romstage.c | 4 +- src/mainboard/asrock/e350m1/romstage.c | 4 +-
sb800: Move headers from SbEarly.h to sb_cimx.h
src/southbridge/amd/cimx/sb800/SbEarly.h | 37 - src/southbridge/amd/cimx/sb800/sb_cimx.h | 47 + src/southbridge/amd/cimx/sb800/early.c | 22 +- src/southbridge/amd/cimx/sb800/late.c | 218 ++---
sb800: Add South Bridge CIMx ramstage entry point wrappers
Wrapper routines sb_Before_Pci_Init, sb_After_Pci_Init, sb_Mid_Post_Init, sb_Late_Post which will be called from northbridge.c, late.c, get_bus_conf.c
src/southbridge/amd/cimx/sb800/late.c | 218 ++--- src/southbridge/amd/cimx/sb800/sb_cimx.h | 47 +
sb800: Reorganise late.c southbridge initialization calls
Do not call southbridge device routines directly from pci ops/enable/init hooks. Call sb_Before_Pci_Init from last sb800 device enable call.
src/southbridge/amd/cimx/sb800/late.c | 218 ++---
sb800: Do not set _RAMSTAGE_ in late.c
src/southbridge/amd/cimx/sb800/late.c | 218 ++---
sb800: Add LPC debug printout
src/southbridge/amd/cimx/sb800/lpc.c | 8 +-
sb800: Add SMBUS debug printout
src/southbridge/amd/cimx/sb800/smbus.c | 19 +
cimx: Create CONFIG_AMD_SB_CIMX
Create CONFIG_AMD_SB_CIMX which will be used to conditionally compile the appropriate calls to SB wrapper code
src/southbridge/amd/cimx/Kconfig | 4 + src/southbridge/amd/cimx/sb800/Kconfig | 2 + src/southbridge/amd/cimx/sb900/Kconfig | 2 +
sb800: Call sb_Late_Post wrapper from from mainboards' get_bus_conf
src/mainboard/advansus/a785e-i/get_bus_conf.c | 7 + src/mainboard/amd/inagua/get_bus_conf.c | 7 + src/mainboard/amd/persimmon/get_bus_conf.c | 7 + src/mainboard/asrock/e350m1/get_bus_conf.c | 7 + src/mainboard/amd/inagua/Makefile.inc | 3 +-
family14: Call southbridge cimx wrapper code from northbridge code
For southbridge AMX cimx call sb_After_Pci_Init and sb_Mid_Post from domain_enable_resources before agesawrapper_amdinitmid
src/northbridge/amd/agesa/family14/northbridge.c | 9 +
family10: Call southbridge cimx wrapper code from northbridge code
For southbridge AMX cimx call sb_After_Pci_Init and sb_Mid_Post from cpu_bus_init
src/northbridge/amd/amdfam10/northbridge.c | 7 +
sb800: Create sb800 platform default config and mainboard specific configs
src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 4 +-
sb800: Add debug printout
src/southbridge/amd/cimx/sb800/cfg.c | 19 +-
sb800: Correct typo CINFIG->CONFIG
src/southbridge/amd/cimx/sb800/cfg.c | 19 +-
sb800: Create 3 new mainboard specific config defines
Create mainboard specific configs NB_SB_GEN2, SB_GPP_GEN2, GEC_CONFIG
src/southbridge/amd/cimx/sb800/cfg.c | 19 +-
sb800: Set port present for all GPP ports in config
sb_config->PORTCONFIG[n].PortCfg.PortPresent = 1 [??? they are reset later according to lane config]
src/southbridge/amd/cimx/sb800/cfg.c | 19 +-
sb800: Create mainboard local sb800 configs
src/southbridge/amd/cimx/sb800/cfg.h | 196 ---- src/mainboard/advansus/a785e-i/platform_cfg.h | 222 ++++ src/mainboard/amd/inagua/platform_cfg.h | 222 ++++ src/mainboard/amd/persimmon/platform_cfg.h | 222 ++++ src/mainboard/asrock/e350m1/platform_cfg.h | 222 ++++
sb900: Create sb900 platform default config and mainboard specific configs
src/southbridge/amd/cimx/sb900/Makefile.inc | 6 +- src/southbridge/amd/cimx/sb900/SbPlatform.h | 4 +- src/southbridge/amd/cimx/sb900/cfg.c | 306 ++++++ src/southbridge/amd/cimx/sb900/early.c | 1 - src/southbridge/amd/cimx/sb900/late.c | 1 -
torpedo: Create mainboard specific sb900 config
src/mainboard/amd/torpedo/cfg.c | 307 ------ src/mainboard/amd/torpedo/cfg.h | 1242 ---------------------- src/mainboard/amd/torpedo/platform_cfg.h | 1240 +++++++++++++++++++++ src/mainboard/amd/torpedo/Makefile.inc | 2 -
torpedo: Fix compiler warnings [?]
src/mainboard/amd/torpedo/BiosCallOuts.c | 5 +-
sb800: Rename structure tag _SB_CPUID_DATA as _CPUID_DATA
Rename structure tag _SB_CPUID_DATA as _CPUID_DATA for consistency with type name CPUID_DATA. [and INconsistency with sb900..]
src/southbridge/amd/cimx/sb800/Amd.h | 2 +-
sb800: Remove IN and OUT from CpuidRead [why do that ?]
src/vendorcode/amd/cimx/sb800/AMDSBLIB.h | 3 +-
cimx: Place #ifndef around BIOS_SIZE define
src/vendorcode/amd/cimx/sb800/OEM.h | 4 +- src/vendorcode/amd/cimx/sb900/Oem.h | 4 +-
sb800: Compile get_sbdn only if CONFIG_RAMINIT_SYSINFO is set
src/southbridge/amd/cimx/sb800/early.c | 22 +-
68 files changed, 2880 insertions(+), 2562 deletions(-)