Myles Watson escribió:
On Tue, Dec 22, 2009 at 9:22 AM, Knut Kujat <knuku@gap.upv.es mailto:knuku@gap.upv.es> wrote:
Hello, as Myles suggested to disable siblings to see if I can pass through this weird exception and the impossibility to do so because of the compile error I changed the physical cpu option to 1 and it worked! But increasing it back to 2 or 4 made the exception come back again. I told you, Myles, I increased stack size to 4000 that was a filthy lie because I thought I'm increasing it to 4000 what I didn't see was that the same option was repeated at the end of the Options.lb file with STACK_SIZE=8000It's always good to check targets/vendor/board/build/fallback/ldoptions to see what's really being used.
(So I don't know why the printks started working). Now fooling around with stack size and setting it up to 10000 all 4 cpus started working and I got a grub menu :) in text mode :( so I have a graphics Initializing faild and Linux doesn't boot up completly.Great. I think we're getting to where we should add your board to the tree. Then we can see the device tree too.
I attached it.
I attached a complete log file, it is not so complete because the first lines of linux boot up are missing because I had to change serial speed on minicom. Thats because I'm having trouble of setting a speed and getting a total different one. Now I thing that my device tree is not completely working and thats why linux got some collusion at the beginning ??It device 0:02.3 isn't getting a driver. 1:06.0 is not found.
PCI: 08:01.0 Hypertransport link capability not foundPCI: pci_scan_bus for bus 08
That doesn't look good.
PCI: Left over static devices: PCI: 08:01.0 PCI: 08:01.1 PCI: 08:02.0
And I have no idea why graphic mode doesn't work since it looks like it finds vga without any problem.VGA: PCI: 00:18.0 (aka node 0) link 2 has VGA device
That doesn't look right. I would think it's on link 0. I don't know why that's set wrong, but it would explain why it's not working.
Thanks, Myles
## ## This file is part of the coreboot project. ## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu yinghailu@amd.com for AMD. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
## CONFIG_XIP_ROM_SIZE must be a power of 2. # for testing with -O != s. FIXME #default CONFIG_XIP_ROM_SIZE = 128 * 1024 default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/failovercalculation.lb
arch i386 end
## ## Build the objects we have code for in this directory. ##
driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o
if CONFIG_GENERATE_MP_TABLE object mptable.o end if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
if CONFIG_USE_INIT makerule ./auto.o depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@" end end
if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end end end
## ## Build our 16 bit and 32 bit coreboot entry code ## if CONFIG_HAVE_FAILOVER_BOOT if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end end
mainboardinit cpu/x86/32bit/entry32.inc
if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end
if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end
## ## Build our reset vector (This is where coreboot is entered) ## if CONFIG_HAVE_FAILOVER_BOOT if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds end else if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds end end
## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds
## ## ROMSTRAP table for MCP55 ## if CONFIG_HAVE_FAILOVER_BOOT if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end end
## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc
### ### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### if CONFIG_HAVE_FAILOVER_BOOT if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end
## ## Setup RAM ## if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end
## ## Include the secondary Configuration files ## config chip.h
dir /southbridge/nvidia/mcp55
chip northbridge/amd/amdfam10/root_complex device apic_cluster 0 on chip cpu/amd/socket_F_1207 device apic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdfam10 #mc0 device pci 18.0 on end device pci 18.0 on end device pci 18.0 on # SB on link 2.0 chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end end end device pci 1.1 on # SM 0 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end end chip drivers/generic/generic #dimm 2-0-0 device i2c 58 on end end chip drivers/generic/generic #dimm 2-0-1 device i2c 59 on end end chip drivers/generic/generic #dimm 2-1-0 device i2c 5a on end end chip drivers/generic/generic #dimm 2-1-1 device i2c 5b on end end chip drivers/generic/generic #dimm 3-0-0 device i2c 5c on end end chip drivers/generic/generic #dimm 3-0-1 device i2c 5d on end end chip drivers/generic/generic #dimm 3-1-0 device i2c 5e on end end chip drivers/generic/generic #dimm 3-1-1 device i2c 5f on end end
end # SM device pci 1.1 on # SM 1 #PCI device smbus address will diepend on addon pci device, do we need to scan_smbus_bus? # chip drivers/generic/generic #PCIXA Slot1 # device i2c 50 on end # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end # end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end # end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end # end # chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 54 on end # end # chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 55 on end # end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end end
end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI device pci 6.0 on end end device pci 6.1 off end # AZA #device pci 8.0 on end # NIC #device pci 9.0 on end # NIC device pci a.0 on end # PCI E 5 #device pci 0.0 on #nec pci-x #end #device pci 0.1 on #nec pci-x # device pci 4.0 on end #scsi # device pci 4.1 on end #scsi #end #ind device pci b.0 on end # PCI E 4 device pci c.0 on end # PCI E 3 device pci d.0 on end # PCI E 2 device pci e.0 on end # PCI E 1 device pci f.0 on end # PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end device pci 19.0 on end device pci 19.0 on end device pci 19.0 on chip southbridge/amd/amd8132 device pci 1.0 on end device pci 1.1 on end device pci 2.0 on device pci 3.0 on end device pci 3.1 on end end end #amd8132 end #device pci 19.0 device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end device pci 19.4 on end device pci 1a.0 on end #link 0 device pci 1a.0 on end #link 1 device pci 1a.0 on end #link 2 device pci 1a.1 on end device pci 1a.2 on end device pci 1a.3 on end device pci 1a.4 on end device pci 1b.0 on end #link 0 device pci 1b.0 on end #link 1 device pci 1b.0 on end #link 2 device pci 1b.1 on end device pci 1b.2 on end device pci 1b.3 on end device pci 1b.4 on end end # mc0 end # PCI domain # chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem # device pnp 0.3 off end # cpuid # device pnp 0.4 on end # smbus_regs_all # device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io # end end #root_complex