On Fri, 2005-01-21 at 10:11 -0800, Al Hooton wrote:
(yet?). At this point, I'm curious as to whether this lspci output matches the EPIA 800 boards you have running LB in-house?
Hold off on that request. I've gotten through LB to my payload. Mark's pointer to the defines at the top of raminit.c were the clue. Turns out I have CAS latency 2 sdram in this particular box, but I hadn't bothered to notice that.
Ron: What do you believe is involved in updating raminit.c for the vt8601 northbridge in order to auto-detect CL of 2 or 3? What about updating it to auto-detect PC100/PC133? I'm not familiar with the register interfaces in the vt8601, I've never seen the specs. What were the chipset bugs you had to work around with the #defines for these two settings back when the code was first put together?
Thanks to everyone that lent a hand! Now, I'm off to figure out why filo can't see my ide drives... 8^(
-Al