Hi,
if we are sure it is behind 15.2 - one can also try to make it hidden. This way the device will be enabled no matter what. If that solves the problem - you need to investigate why coreboot does not enable the device.
Best,
Chris
On 10/16/20 3:05 PM, Peter Stuge wrote:
Paul Menzel wrote:
With the vendor firmware 6601, it is
04:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd.RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] (rev 09)
behind PCI bridge 00:15.2.
..
In the current state [1], coreboot says device 00:15.2 is disabled
Show all devs... After init.
..
PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 0
But it is enabled in the devicetree `src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb`.
device pci 15.2 on end # PCI bridgespew log
..
Enabling cache Setting up local APIC... apic_id: 0x11 done. siblings = 01, CPU #1 initialized All AP CPUs stopped (1060 loops) CPU0: stack: 0x5fef4000 - 0x5fef5000, lowest used address 0x5fef455c, stack used: 2724 bytes CPU1: stack: 0x5fef3000 - 0x5fef4000, lowest used address 0x5fef3dbc, stack used: 580 bytes CPU_CLUSTER: 0 init finished in 64 msecs PCI: 00:00.0 init PCI: 00:00.0 init finished in 0 msecs
..
PCI: 00:15.0 init PCI: 00:15.0 init finished in 0 msecs PCI: 00:15.1 init PCI: 00:15.1 init finished in 0 msecs PCI: 00:18.1 init PCI: 00:18.1 init finished in 0 msecs
Note that there is no init for 15.2 above. I don't know why, if it's enabled in the mainboard devicetree file.
Another thought - have you compared PCI bus numbers and addresses between vendor BIOS and coreboot? They can change around, certainly bus numbers but wasn't there a thread a while back with addresses being confused too?
Sorry I can't suggest anything more concrete
//Peter _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org